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We present an advanced CMOS integration scheme based on embedded SiGe (eSiGe) with a novel graded germanium process. The retention of channel strain enabled a pFET performance gain of 15% over a non-graded eSiGe control. When combined with a compressive stress liner (CSL), the pFET drive current reached 770muA/mum at Ioff = 100nA/mum with VDD = 1V. Competitive nFET performance was maintained. Parasitics...
An optimized 4-way stress integration on partially-depleted SOI (PD-SOI) CMOS is presented. An embedded-SiGe process and a compressive-stressed liner film are used to induce compressive strain in the PMOS (PMOS "stressors"). A stress memorization process and a tensile-stressed liner film are used to induce tensile strain in the NMOS (NMOS "stressors"). With optimization, the different...
The effects of the integration of two major PFET performance enhancers, embedded SiGe (e-SiGe) junctions and compressively stressed nitride liner (CSL) have been examined systematically. The additive effects of e-SiGe and CSL have been demonstrated, enabling high performance PFET (drive current of 640 muA/mum at 50 nA/mum off state current at 1V) with only modest Ge incorporation (~20 at. %) in S/D...
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