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Through Silicon Interposer (TSI) needs to fulfill multi-die stacking in one packaging which can bring high integration density, short interconnection length and small size for next generation devices. Die stacking is a key process in the TSI manufacturing flow, and within that process, die warpage is of central concern. This is because the large warpage of the Si-mterposer induces poor joining of...
For the first time, Ge CMOS with all thermal processes performed by microwave annealing (MWA) has been realized. The full MWA process is under 390 oC. It significantly outperforms conventional rapid thermal annealing (RTA) process in 3 aspects: (1) Diffusion-less junction: for easily diffused n-type dopant, phosphorous (P), the ion implantation dopant profile after the MWA activation process remains...
When the flip-chip packaging has been moving to the lead-free, fine-pitch and high-current-density packaging, the flip chip with copper-pillar-bump interconnects can provide a solution to this need. However, this package during the thermal cycling test (TCT) still suffers the reliability problems such as delamination at the Cu low-k materials or at the interface between the UBM (under bump metallurgy)...
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