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For the first time, we report a scalable technique to fabricate graphene transistors with self-aligned buried gates process. The high performance buried-gate graphene transistor has excellent field-effect mobility of 6,100cm2/V·s and 24,000 cm2/V·s before and after subtraction of contact resistance. To the best of our knowledge, this is the highest room temperature mobility for CVD graphene FETs reported...
Tunnel field-effect transistors (TFETs) can potentially achieve sub-60-mV/dec SS, but their performance strongly depends on the dopant profile at the tunneling junction. In this paper, very sharp (~.2 nm/dec) optimized tunneling-junction dopant profile for the silicon p-n-p-n TFET is demonstrated by molecular beam epitaxial growth. Devices are fabricated with a low-thermal-budget ( <; 620°C) vertical...
An integrated Ge-on-SOI photo-detector based on secondary photo-conductivity is proposed and demonstrated. A 1 mW beam at 1.55 mum creates charge separation in the Ge thereby changing the resistivity of the underlying Silicon by ~3%.
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