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A solution of utilizing an N-rich SiON gate dielectric toward achieving highly reliable pMOS is demonstrated. The solution consists of a combination of two techniques: (1) a SiN-based gate dielectric with oxygen-enriched interface (OI-SiN) enabling nMOS and pMOS characteristics superior to plasma-nitrided oxides (PNO) and (2) a dual-core-SiON technique in which SiON in pMOS is selectively thickened...
In this paper, the authors demonstrate the improvement of HfSiON pFET characteristics with F incorporation technique, which might be a powerful tool to lower Vth in pFET with both poly-Si and PC-FUSI gate. Using F implantation in channel region prior to HfSiON formation Vth lowering up to ~200mV is obtained without mobility degradation. Furthermore, impact of F incorporation in HfSiON is investigated...
A technique for optimizing ultra-thin (EOT ~ 1.1-1.3 nm) SiON gate dielectrics independently for n- and p-MOSFETs is demonstrated. Selective nitrogen-enrichment for the nMOS and fluorine incorporation to the pMOS regions were both performed by ion implantation into the Si-substrate with resist masks before gate oxidation. The former provided suppression of gate leakage current and enhancement of drain...
F incorporation into HfSiON dielectric using channel implantation technique is shown to be highly effective in lowering Vth and improving NBTI in poly-Si gate pFET. Mobility degradation is not accompanied and drive current is increased by 180%. From analytical and electrical characterization, the Vth shift is attributed to change in trap density
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