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In this paper, the trade-off between device mismatch, quantization noise and device noise in successive approximation register analog to digital converter (SAR ADC) is investigated. An optimization method for designing area-constrained SAR ADC with highest possible energy efficiency for a given dynamic range (DR) is proposed. By taking device noise and process mismatch information into account, it...
In this paper a low-power low-noise amplifier for neural recording and biomedical applications is presented. The frequency band of the amplifier is tunable. It has a gain of 28.3 dB. The low and the high cut-off frequency can be adjusted from 24 mHz to 30.6 Hz and 4.5 kHz to 7.47 kHz, respectively. The circuit is designed in 0.18μm CMOS process, and it consumes only 77.8 nW at 1.8V supply voltage...
This paper presents an inductor-less low-noise amplifier (LNA) design for ultra-wideband (UWB) receivers and microwave access covering the frequency range from 0.4 to 5.7 GHz using 0.18-μm CMOS. Simulation results show that the voltage gain reaches a peak of 18.94 dB in-band with an upper 3-dB frequency of 5.7 GHz. The IIP3 is about -3 dBm and the noise figure (NF) ranges from 3.15-3.86 dB over the...
This paper presents a transmitter design for Ultra Wideband Impulse Radio (UWB-IR) communications. The design is targeted towards the implementation of passive Wireless Sensor Tags (WST) where micro-power consumption is required. The transmitter has been implemented in UMC 0.18μm CMOS and placed inside a QFN lead-less package. It complies with the FCC regulations for Pulse Rate Frequencies (PRF) up...
In this paper, a reconfigurable, low-power Application Specific Integrated Circuit (ASIC) that extracts and transmits electrocardiograph (ECG) signals is presented. An intelligent electrode is introduced which consists of the proposed ASIC and a micro spike array, permitting onsite ECG signal acquisition, processing and transmission. Fabricated in a standard 0.18 mum CMOS process, the ASIC consumes...
In this work, a 10 Mb/s impulse UWB RFID tag in 0.18 mum CMOS is presented. The tag is remotely powered by a UHF signal with a minimum input RF power as low as 14.1 muW. The primary innovation is to employ two different communication links (UWB and UHF) respectively in the uplink and downlink of the tag. This is because the amount of data or instructions from a reader to a tag is small and as a result...
In this paper we present a power management and a clock generator for a novel passive UWB tag. It can be used in many applications such as radio frequency Identification (RFID), and ubiquitous wireless sensing. As same as conventional RFID, the tag captures the power from the incoming RF signal, converts to DC and stores it in a relatively big capacitor. A voltage sensor and a regulator provide stable...
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