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Crosstalk is an increasingly significant effect for VLSI timing performance. Traditional STA or SSTA techniques provide pessimistic crosstalk analysis based on timing window envelopes. In this paper, we present input-aware signal probability-based statistical timing analysis (SPSTA) taking crosstalk-induced delay variations into account. SPSTA achieves reduced pessimism and improved accuracy by signal...
Nanoscale VLSI systems are subject to an ever increasing performance variability, which hinders performance scaling and increases verification complexity. In this paper, we study an often neglected source of performance variability, namely logic inputs or system workload. We present input-aware statistical timing analysis, which gives not only critical path delays but also critical path activating...
Estimating the dynamic powers is crucial for power and energy efficient chip designs. With increasing variability from manufacture processes, dynamic powers can manifest significant variations due to uncertainties in device geometry and delay variations. In this paper, we propose a new statistical dynamic power estimation method considering the spatial correlation in process variation. We first show...
VLSI timing analysis and power estimation target the same circuit switching activity. Power estimation techniques are categorized as (1) static, (2) statistical, and (3) simulation and testing based methods. Similarly, statistical timing analysis methods are in three counterpart categories: (I) statistical static timing analysis, (2) probabilistic technique based statistical timing analysis, and (3)...
Statistical timing analysis needs a priori knowledge of process variations. Lack of such a priori knowledge of process variations prevents accurate statistical timing analysis, for which foundry confidentiality policy has largely been blamed. A significant part of process variations are design specific, and can only be extracted from production chip performance statistics. In this paper, the author...
We propose gate level statistical simulation to bridge the gap between the most accurate Monte Carlo SPICE simulation and the most efficient circuit level statistical static timing analysis (SSTA) for a new level of efficiency-accuracy tradeoff. Our method is based on (1) a multi-point waveform characterization by signal arrival times at multiple voltage thresholds, (2) a parameterized current source...
Current source based gate models achieve orders of magnitude of improved accuracy than the previous voltage source and effective load capacitance based gate models. Increasingly significant variability in DSM and nanometer scale VLSI designs calls for statistical analysis and optimization. In this paper, we propose a more efficient statistical gate level simulation method than Monte Carlo simulation...
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