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In this paper, a large 2.5D glass interposer is demonstrated with 50 um chip-level interconnect (FLI), 3/3 um line and space (L/S) escape routing, and six metal layers, which are targeted for JEDEC high bandwidth memory (HBM). Our routing design suggests that double sided panel processing with 3/3 um L/S can accommodate required signal lines for HBM. Then, 3/3 um L/S transmission lines on 25mm × 30mm...
This paper describes the first design and fabrication of a large 2.5D glass interposer with 50 μm pitch chip-level interconnections made of 6 layers of 3 μm re-distribution (RDL) wiring. Many applications including high-performance networking and cloud computing data centers require ultra-high-bandwidth of the magnitude of 512 GB/s. Silicon-based 2.5D interposers are the only approaches being pursued...
This paper presents the first demonstration of polycrystalline silicon interposers with fine pitch through package vias (TPV), with less than 5μm RDL lithography at 50μm pitch copper microbump assembly. Silicon interposers with through silicon vias (TSV) and back end of line (BEOL) wiring offer compelling benefits for 2.5D and 3D system integration; however, they are limited by high cost and high...
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