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Software Defined Networking (SDN) enables network innovation and brings flexibility by separation of the control and data planes and logically centralized control. However, this network paradigm complicates flow rule management. Current approaches generally install rules reactively after table misses or pre-installs them by flow prediction. Such approaches consume nontrivial network resources during...
Convolutional neural networks (CNNs) have recently broken many performance records in image recognition and object detection problems. The success of CNNs, to a great extent, is enabled by the fast scaling-up of the networks that learn from a huge volume of data. The deployment of big CNN models can be both computation-intensive and memory-intensive, leaving severe challenges to hardware implementations...
Emerging memory devices enable performance improvements in memory applications and make possible chip designs using beyond von Neumann architectures. This paper explores the use of emerging memory devices in applications of nonvolatile logics and neuromorphic computing, and provides a review of several silicon examples of nonvolatile logics. This paper also discusses the challenges involved in the...
The training of neural network (NN) is usually time-consuming and resource intensive. Memristor has shown its potential in computation of NN. Especially for the metal-oxide resistive random access memory (RRAM), its crossbar structure and multi-bit characteristic can perform the matrix-vector product in high precision, which is the most common operation of NN. However, there exist two challenges on...
In this work, we study the problem of keeping the objective functions of individual agents ∊-differentially private in cloud-based distributed optimization, where agents are subject to global constraints and seek to minimize local objective functions. The communication architecture between agents is cloud-based - instead of communicating directly with each other, they coordinate by sharing states...
Convolutional Neural Network (CNN) has become a successful algorithm in the region of artificial intelligence and a strong candidate for many applications. However, for embedded platforms, CNN-based solutions are still too complex to be applied if only CPU is utilized for computation. Various dedicated hardware designs on FPGA and ASIC have been carried out to accelerate CNN, while few of them explore...
Developing heterogeneous system with hardware accelerator is a promising solution to implement high performance applications where explicitly programmed, rule-based algorithms are either infeasible or inefficient. However, mapping a neural network model to a hardware representation is a complex process, where balancing computation resources and memory accesses is crucial. In this work, we present...
Software-Defined Networking (SDN) is a brand-new networking technology which promises to provide flexible architecture and power features. However, performance is always a major concern in deploying SDN. In this paper, we demonstrate how a naive SDN network may suffer from long delay for the first packet in a session, and we propose a "Look Ahead Mechanism" to shorten the delay time. In...
Memristor-based neuromorphic computing system provides a promising solution to significantly boost the power efficiency of computing system. Memristor-based neuromorphic computing system has a wide range of design choices, such as the various memristor crossbar cell designs and different parallelism degrees of peripheral circuits. However, a memristor-based neuromorphic computing system simulator,...
Deep Learning (DL) is becoming popular in a wide range of domains. Many emerging applications, ranging from image and speech recognition to natural language processing and information retrieval, rely heavily on deep learning techniques, especially the Neural Networks (NNs). NNs have led to great advances in recognition accuracy compared with other traditional methods in recent years. NN-based methods...
The key to high performance for GPU architecture lies in massive threading to drive the large number of cores and enable overlapping of threading execution. However, in reality, the number of threads that can simultaneously execute is often limited by the size of the register file on GPUs. The traditional SRAM-based register file costs so large amount of chip area that it cannot scale to meet the...
With the exponential growth of data size, data storage and analysis have been exposed to more challenges due to the lack of disk capacity and the limited network bandwidth. Data compression technique provides a good solution to mitigate these effects. In this paper, we propose a self-aware data compression system on FPGA for typical data warehousing, such as Hive, with column stored data and multi-threading...
This paper presents a field programmable gate array (FPGA) based 2-dimentional hand gesture recognition system using Haar feature Adaboost detector, skin color segmentation, and frame subtraction background modeling. The system obtains detection results and tracking results simultaneously. In addition, the interaction instructions are interpreted by a judgment strategy. The proposed system can complete...
In this paper, we describe a research prototype conceived to demonstrate how subscriber analytics can be used to personalize mobile broadband (MBB) offers. The concept relies on the fact that i) the mobile networks are underutilized in certain areas during certain periods and highly loaded in others and ii) the contribution of different subscribers to the network utilization also differs, which can...
The emerging neuromorphic computation provides a revolutionary solution to the alternative computing architecture and effectively extends Moore's Law. The discovery of the memristor presents a promising hardware realization of neuromorphic systems with incredible power efficiency, allowing efficiently executing the analog matrix-vector multiplication on the memristor crossbar architecture. However,...
Placement is one of the most important techniques in modern field-programmable gate array design. Generally, analytical placement method optimizes the wire-length in global stage while allowing overlaps between blocks and is followed by a legalization step to remove all overlaps. In this paper, we propose a window based legalization method to remove all overlaps and place all instances at legalized...
Nowadays, Graphics Processing Unit (GPU), as a kind of massive parallel processor, has been widely used in general purposed computing tasks. Although there have been mature development tools, it is not a trivial task for programmers to write GPU programs. Based on this consideration, we propose a novel parallel computing architecture. The architecture includes a parallel programming model, named Gemma,...
Volunteer computing has recently received the strong attraction for executing high throughput applications as CPU, storage and network capacities improve and become cheaper. Volunteer resource can provide computing power for cloud computing in many respects, but there is no general survey for appraisal of the suitability of the organization's structure and resources. Therefore, we propose a new comprehensive...
This paper presents a modified pipeline single-path delay feedback (SDF) fast Fourier transform (FFT) architecture. The canonic signed digit (CSD) representation is used to design the function of complex multiplier, which is the main function block in the FFT processor. The processor of a 16-bit 16-point pipeline FFT is realized on the Xilinx Virtex-4 FPGAs. The achieved maximum clock frequency is...
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