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Ring Oscillator (RO) Physical Unclonable Function (PUF) is one of the most popular silicon PUFs which exploit manufacturing variations during the chip fabrication process. RO PUF can generate secret bits by comparing the frequency difference between two ROs. However, previous RO PUFs improve flexibility and reliability through adding redundant ROs and thus incur unacceptable hardware overheads. In...
Physical Unclonable Function (PUF) is one of the most efficient technique to generate unique and random identification for chip authentication. Ring oscillator (RO) PUF takes advantage of delay variations of a pair of ROs, which is easy to implement on FPGAs. An important consideration for FPGA based RO PUF is how to eliminate systematic variation without reducing the number of output bits. To address...
Physical Unclonable Function (PUF) makes use of the uncontrollable process variations during the production of IC to generate a unique signature for each IC. It has a wide application in security such as FPGA Intellectual Property (IP) protection, key generation and digital rights management. Ring Oscillator (RO) based PUF and Arbiter-based PUF are the most popular PUFs, but they are not specially...
Rewiring is a useful technique that perturbs the logic of Look-Up Tables (LUTs) without changing the functions of circuits. This internal logic perturbation can be used to trade for critical LUT-external logic/wire removals for EDA improvements. In this paper, we design a flow of embedding the rewiring engine into routing process for FPGA improvement. In our design, we change the priorities of target...
This paper considers the problem of lookup table (LUT) based FPGA technology mapping for power minimization in combinational circuits. The problem has been previously proved to be NP-hard, and hence we present an efficient heuristic algorithm, PowerMap_er. This paper describes a technique that reduces power consumption by reducing the edge count in mapped network. The purpose of this technique is...
Recent generation of FPGA devices takes advantage of speed and density benefits resulted from heterogeneous FPGA architecture, in which several basic LUTs can be combined to form one larger size LUT called macro. Large macros not only decrease network depth efficiently but also reduce area. In this paper, a new technology mapping algorithm, named MacroMap is proposed for the heterogeneous FPGAs with...
Nowadays, FPGA architecture has been improved rapidly, and more and more hard structures are integrated on heterogeneous FPGA chips. RTL technology mapping is one of methods to solve the problem of making use of those hard structures efficiently. However, the traditional RTL mapping tools can not do optimization on the delay on interconnect wires which can not be ignored in the current integrated...
As the technology migrates into ultra deep sub-micron era, the critical dimension of the circuits has become smaller than the lithographic wavelength. Due to the unavoidable diffraction and interaction phenomena of sub-wavelength technologies, the deformations between the image on wafer and layout have become one of the major factors in performance and yield rate. Optical proximity correction is one...
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