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An SST transmitter is described with ground regulation, P-to-N shunting and partially weighted segments for fine granularity level/equalization. Clocks and datapath dissipate 32mW at 7.4Gb/s with an 800mV eye for a power efficiency of 4.32mW/(Gb/s). Measured total jitter is 209.6mUI or 28.3ps at 10-12 BER. Target protocols include PCIe G1/2, XAUI, FC 1/2/4, CEI6 MR and SATA 1/2.
A 14-bit 100-MS/s pipelined ADC in 0.18 mum 1P6M CMOS process is presented. A new sampling technique is introduced which achieves high linearity over wide bandwidth by eliminating the major sources of distortion at low and high input frequencies. The ADC uses digital background calibration, featuring a shuffled-dithering scheme, to obtain a DNL of +0.18/-0.18 LSB and an INL of +1.1/-0.6 LSB. It achieves...
This paper is concerned with the design of a high speed current steering DAC. Techniques to improve static precision are preserved while their negative influences on dynamic performance are suppressed. The prototype is implemented with the SMIC 0.13 ??m process. With an update rate of 700 Msamples/s, measurements show that the DAC achieves over 40 dB SFDR under a sampling rate of 700 Ms/s and consumes...
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