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In PLDs, the connections from the CLB inputs and LUT outputs to the LUT inputs are often formed with a full crossbar. Such a high degree of connectivity makes routing easier, but it has significant area overhead. This chapter explores the use of sparse crossbars as an alternative switch matrix inside the clusters. This organisation is called a sparse cluster architecture. The experimental results...
Before embarking upon the design of programmable logic interconnect, it is inspiring and informative to reflect back on the design of interconnection networks in general. Interconnections networks have original foundations in telephony, and from this spawned a great deal of research in computer systems networks, parallel systems design, and graph theory. Rather than present a thorough treatment of...
Programmable logic devices provide a simple abstraction that permits digital system design to be completed at the RTL level. This abstraction conveniently hides from the designer an increasing number of physical design problems which are addressed at the PLD design stage instead. As a result, it is a promising way to cope with ever-increasing design costs.
This chapter presents a number of sparse crossbar designs and a general method for evaluating and constructing sparse crossbars is developed. The construction method produces highly routable sparse crossbars which are area-efficient. The evaluation method uses a Monte Carlo technique to estimate the percentage of random test vectors that can be routed. The routability of each test vector is determined...
This chapter describes the models, methodology and tools used to evaluate PLD routing networks. The PLD architectural model is described first, including a detailed account of the area and delay models used as performance metrics. Next, the general experimental methodology and CAD tool flow for evaluating PLD performance is given.
This chapter presents an analytical framework which considers the design of a continuous fabric of switch blocks containing any length of wire segments. The framework is used to design new switch blocks which are experimentally shown to be as effective as the best ones known to date. With this framework, we hope to inspire new ways of looking at switch block design.
In commercial PLDs, buffers have recently replaced pass transistors as the preferred type of routing switch. This chapter investigates interconnect that mixes these two switch types together. The goals of this study are twofold: to reduce area by replacing a number of buffered switches with pass transistors and to reduce delay by allowing a signal to alternate between a buffer and a pass transistor...
The rapid advancement of semiconductor technology has required the concurrent advancement of the digital systems design process. For example, early integrated circuits such as the Intel 4004 processor were completely hand-designed, including the layout artwork. This was a reasonable effort for a 2,300-transistor device built in 1971 with a 10µm technology process [Int02]. In contrast, the latest Intel...
Programmable Logic Devices (PLDs) have become the key implementation medium for the vast majority of digital circuits designed today. While the highest-volume devices are still built with full-fabrication rather than field programmability, the trend towards ever fewer ASICs and more FPGAs is clear. This makes the field of PLD architecture ever more important, as there is stronger demand for faster,...
This paper presents VENICE, a new soft vector processor (SVP) for FPGA applications. VENICE differs from previous SVPs in that it was designed for maximum throughput with a small number (1 to 4) of ALUs. By increasing clockspeed and eliminating bottlenecks in ALU utilization, VENICE can achieve over 2x better performance-per-logic block than VEGAS, the previous best SVP. While VENICE can scale to...
VENICE is a new soft vector processor (SVP) for FPGA applications that is designed for maximum through-put with a small number (1 to 4) of ALUs. By increasing clock speed and eliminating bottlenecks in ALU utilization, VENICE achieves over 2x better performance-per-logic block than VEGAS, the previous best SVP. VENICE is also simpler to program, as its instructions use standard C pointers into a scratchpad...
This article consists of a collection of slides from the author's conference presentation on VENICE (Vector Extensions to NIOS Implemented Compactly and Elegantly), a SVP (soft vector processor) intended to accelerate computationally intensive applications implemented on an FPGA. SVPs are exclusively for FPGAs, targeted at the productivity gap between writing custom hardware in an HDL and writing...
Each new semiconductor technology node brings smaller, faster transistors and smaller, slower wires. In particular, long interconnect wires in modern FPGAs now require rebuffering at interior points in the wire. This paper presents a framework for designing and evaluating long, buffered interconnect wires in FPGAs with near-optimal delay performance using HSPICE-derived delays. Given a target physical...
FPGA architects are always searching for more benchmark circuits to stress CAD tools and device architectures. In this paper we present a new heuristic to generate benchmark circuits specifically for incremental place and route tools. The method removes part of a real circuit and replaces it with a modified version of the same circuit to mimic an incremental design change. The generation procedure...
Each new semiconductor technology node brings smaller transistors and wires. Although this makes transistors faster, wires get slower. As FPGA device designers strive to obtain the lowest possible circuit delays from a given technology node, they must take an increasingly interconnect-focused viewpoint in the design process. In particular, for long interconnect wires, signals now require rebuffering...
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