Denis Flandre

article

Li‐Doping and Ag‐Alloying Interplay Shows the Pathway for Kesterite Solar Cells with Efficiency Over 14%

Yuancai Gong, Alex Jimenez‐Arguijo, Axel Gon Medaille, Simon Moser, more

Advanced Functional Materials > 34 > 42 > n/a - n/a

Kesterite photovoltaic technologies are critical for the deployment of light‐harvesting devices in buildings and products, enabling energy sustainable buildings, and households. The recent improvements in kesterite power conversion efficiencies have focused on improving solution‐based precursors by improving the material phase purity, grain quality, and grain boundaries with many extrinsic doping...

article

29.3: Invited Paper: Defect Engineering in n‐Type Oxide Semiconductor TFTs

Guoli Li, Jiawei He, Denis Flandre, Lei Liao

SID Symposium Digest of Technical Papers > 52 > S2 > 400 - 400

article

Comparative Study of Al₂O₃ and HfO₂ for Surface Passivation of Cu(In,Ga)Se₂ Thin Films: An Innovative Al₂O₃/HfO₂ Multistack Design

Romain Scaffidi, Dilara G. Buldu, Guy Brammertz, Jessica de Wild, more

physica status solidi (a) > 218 > 14 > n/a - n/a

In Cu(In,Ga)Se₂ (CIGS) thin‐film solar cells, interface recombination is one of the most important limiting factors with respect to device performance. Herein, metal–insulator–semiconductor samples are used to investigate and compare the passivation effects of Al₂O₃ and HfO₂ at the interface with CIGS. Capacitance–voltage–frequency measurements allow to qualitatively and quantitatively assess the...

article

15.3: Defect Engineering in n‐Type Oxide Semiconductor TFTs

Guoli Li, Jiawei He, Huiru Wang, Denis Flandre, more

SID Symposium Digest of Technical Papers > 52 > S1 > 101 - 101

article

Wafer‐Scale Nanoimprint Lithography Process Towards Complementary Silicon Nanowire Field‐Effect Transistors for Biosensor Applications

Achim Müller, Xuan T. Vu, Vivek Pachauri, Laurent A. Francis, more

physica status solidi (a) > 215 > 15 > n/a - n/a

The authors present a combined, p‐ and n‐type fabrication process for silicon nanowire field‐effect transistor (SiNW FET) biosensors on a 4” wafer format with nanowire widths down to 100 nm and a height of only 42 nm. The full wafer design includes various SiNW FET combinations with metal or electrolyte gate contacts. A top‐down fabrication protocol on high‐quality silicon‐on‐insulator wafers is...

article

Surface Passivation of CIGS Solar Cells Using Gallium Oxide

Siddhartha Garud, Nikhil Gampa, Thomas G. Allen, Ratan Kotipalli, more

physica status solidi (a) > 215 > 7 > n/a - n/a

This work proposes gallium oxide grown by plasma‐enhanced atomic layer deposition, as a surface passivation material at the CdS buffer interface of Cu(In,Ga)Se₂ (CIGS) solar cells. In preliminary experiments, a metal‐insulator‐semiconductor (MIS) structure is used to compare aluminium oxide, gallium oxide, and hafnium oxide as passivation layers at the CIGS‐CdS interface. The findings suggest that...

article

A Robust 10-Gb/s Duobinary Transceiver in 0.13-μm SOI CMOS for Short-Haul Optical Networks

Javier Aguirre, David Bol, Denis Flandre, Carlos Sanchez-Azqueta, more

IEEE Transactions on Industrial Electronics > 2018 > 65 > 2 > 1518 - 1525

Duobinary modulation is a robust and attractive coding format for high-speed serial data transmission because it allows an excellent tradeoff between speed, noise and power. However, conventional architectures reported in the literature performing the necessary precodification in a duobinary transceiver suffer from a severe vulnerability to glitches that limits their performances at high data rates...

article

Intrinsic rectification in common-gated graphene field-effect transistors

Pierre-Antoine Haddad, Denis Flandre, Jean-Pierre Raskin

Nano Energy > 2018 > 43 > C > 37-46

Terahertz rectifying antennas (rectennas) couple micron-size antennas and high-speed diodes to convert the incident electro-magnetic radiation to useable DC power. At such frequencies, the device acting as the diode requires both a nonlinear electrical behavior and a very low parasitic capacitance. Due to their low-capacitance planar structure and high carrier mobility values, several graphene devices...

article

Leakage Current and Low-Frequency Noise Analysis and Reduction in a Suspended SOI Lateral p-i-n Diode

Guoli Li, Valeriya Kilchytska, Nicolas Andre, Laurent A. Francis, more

IEEE Transactions on Electron Devices > 2017 > 64 > 10 > 4252 - 4259

In this paper, we present a detailed analysis of leakage current in a silicon-on-insulator (SOI) lateral P⁺P⁻N⁺ (p-i-n) diode suspended on a microheating platform, combining device experimental characterization and numerical simulation. The diode leakage currents have been extensively studied using the back-gate bias as a means to alter the space-charge (SC) condition at the P⁻ region (I-region)/buried...

chapter

An 80-MHz 0.4V ULV SRAM macro in 28nm FDSOI achieving 28-fJ/bit access energy with a ULP bitcell and on-chip adaptive back bias generation

Thomas Haine, Quoc-Khoi Nguyen, Francois Stas, Ludovic Moreau, more

ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference > 312 - 315

ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference (ESSCIRC)

In this paper, we propose an ultra-low-voltage (ULV) SRAM in 28nm FDSOI based on a 7-T ULP bitcell that allows using only low V_t (LVT) transistors for density and speed without prohibitive leakage. The retention is based on two CMOS negative-differential resistance (NDR) structures. Thanks to importance sampling (IS) methodology, the proposed bitcell has been sized to reach low failure rate for 8-kB...

article

Multiple-Wavelength Detection in SOI Lateral PIN Diodes With Backside Reflectors

Guoli Li, Nicolas Andre, Pierre Gerard, Syed Zeeshan Ali, more

IEEE Transactions on Industrial Electronics > 2017 > 64 > 9 > 7368 - 7376

This research details the potential of a microhotplate photo sensor, based on a silicon-on-insulator (SOI) lateral PIN (P⁺/P^–/N⁺) diode and a microheater, fabricated on a thin suspended membrane from a commercial 1.0-μm SOI complementary metal oxide semiconductor technology. A local annealing (30-min. microheating, at elevated temperature ∼250 °C) is directly carried out onto the suspended diode to...

chapter

Experimental evaluation of mismatching on the analog characteristics of GC SOI MOSFETs

Camila Restani Alves, Marcelo Antonio Pavanello, Michelly de Souza, Denis Flandre

2017 32nd Symposium on Microelectronics Technology and Devices (SBMicro) > 1 - 4

2017 32nd Symposium on Microelectronics Technology and Devices (SBMicro)

This paper presents an experimental study of mismatching on the analog characteristics of fully-depleted graded-channel SOI MOSFET in comparison to uniformly doped transistors. The study is carried out using dedicated structures to account for the mismatch that have been fabricated at the same chip and with the same technology. Important basic parameters such as threshold voltage and subthreshold...

chapter

Comparative experimental study of the improved MOSFETs matching by using the hexagonal layout style

Vinicius Vono Peruzzi, Christian Renaux, Denis Flandre, Salvador Pinillos Gimenez

2017 32nd Symposium on Microelectronics Technology and Devices (SBMicro) > 1 - 4

2017 32nd Symposium on Microelectronics Technology and Devices (SBMicro)

On this study, it is described an experimental comparative analysis of the devices matching regarding a 360 Metal-Oxide-Semiconductor Silicon-On-Insulator (SOI) Field Effect Transistors, n-type (nMOSFETs) sample, which were implemented with a hexagonal (Diamond) and rectangular gate geometries. Considering some relevant electrical parameters studied in the paper, the results indicate that the Diamond...

article

A Quasi-Static Model of Silicon Substrate Effects in Graphene Field Effect Transistors

Pierre-Antoine Haddad, Denis Flandre, Jean-Pierre Raskin

IEEE Electron Device Letters > 2017 > 38 > 7 > 987 - 990

Investigations of the fundamental properties of graphene have leveraged the versatility of the CMOS fabrication platform early on by using oxidized semiconductor substrates with a highly doped back gate to behave as a metal gate down to cryogenic temperatures. For future applications at room temperature and co-integration with standard silicon circuits, standard substrates should be considered and...

chapter

Automated layout-integrated sizing of a 2.45 GHz differential-drive rectifier in 28 nm FDSOI CMOS

Pierre-Antoine Haddad, Francois Stas, Jean-Pierre Raskin, David Bol, more

2017 IEEE Wireless Power Transfer Conference (WPTC) > 1 - 4

2017 IEEE Wireless Power Transfer Conference (WPTC)

Rectifiers are considered key analog blocks to power the energy-autonomous wireless applications envisioned by the Internet-of-Things. However, their design routine is still a time-consuming process as the layout step requires human intervention at each iteration of the optimization phase. The layout parasitic effects (e.g. well-proximity effects) introduced by this step can have a non-negligible...

article

Optimisation of rear reflectance in ultra-thin CIGS solar cells towards >20% efficiency

Olivier Poncelet, Ratan Kotipalli, Bart Vermang, Angus Macleod, more

Solar Energy > 2017 > 146 > C > 443-452

In order to decrease their cost and the use of rare metal elements, thin film solar cell thicknesses are continuously reduced at the expense of their efficiency, due to a lack of absorption for long wavelengths. Optimisation of cells rear reflectance (Rb) thus becomes meaningful to provide non-absorbed light a second chance to be harvested by the active cell layer. In this sense, we present a way...

article

Quantum Efficiency Improvement of SOI p-i-n Lateral Diodes Operating as UV Detectors at High Temperatures

Carla Novo, Rudolf Buhler, Joao Baptista, Renato Giacomini, more

IEEE Sensors Journal > 2017 > 17 > 6 > 1641 - 1648

Thin-film lateral SOI p-i-n diodes can be used as photodetectors especially in the wavelength range of blue and ultra-violet (UV) radiation. Unlike vertical devices, lateral diodes can have depletion regions very close to the device surface, where the absorption of low-wavelengths radiation takes place. Due to this proximity to the surface, an MOS back-gate can control the charge density inside this...

article

Boosting the SOI MOSFET Electrical Performance by Using the Octagonal Layout Style in High Temperature Environment

Egon Henrique Salerno Galembeck, Christian Renaux, Denis Flandre, Saulo Finco, more

IEEE Transactions on Device and Materials Reliability > 2017 > 17 > 1 > 221 - 228

This paper describes an experimental comparative study between the silicon-on-insulator (SOI) metal-oxide-semiconductor (MOS) field effect transistors (MOSFETs) implemented with the octagonal gate geometries and their typical rectangular counterparts operating in high-temperature conditions. The 1

${\mu }\text{m}$

fully depleted SOI complementary metal-oxide semiconductor technology was employed...

chapter

Efficient passive energy harvesters at 950 MHz and 2.45 GHz for 100 μW applications in 65 nm CMOS

Pierre-Antoine Haddad, Jean-Pierre Raskin, Denis Flandre

2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS) > 508 - 511

2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)

Two 2-stage rectifiers are designed at 950 MHz and 2.45 GHz in 65 nm CMOS bulk technology to provide a 100 μW output power under 1 V with 79.9% and 76.6% power conversion efficiency, respectively. A portable and automated design methodology is used here based on foundry models. This methodology is extended to optimize both the cross-coupled and differentialdrive rectifier architectures at UHF by using...

chapter

Low power highly linear temperature sensor based on SOI lateral PIN diodes

Michelly de Souza, Marcelo Antonio Pavanello, Denis Flandre

2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) > 1 - 3

2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)

This work presents a highly linear temperature sensors implemented with SOI Lateral PIN Diodes, for low-power applications, biased on the exponential region of the I-V characteristics. Experimental results are shown for temperatures ranging between 150 K and 400 K, showing that depending on the selected bias currents, the linearity can be improved in comparison to a single SOI PIN diode. Simulations...

INFONA - science communication portal

Search results for: Denis Flandre

Li‐Doping and Ag‐Alloying Interplay Shows the Pathway for Kesterite Solar Cells with Efficiency Over 14%

29.3: Invited Paper: Defect Engineering in n‐Type Oxide Semiconductor TFTs

Comparative Study of Al₂O₃ and HfO₂ for Surface Passivation of Cu(In,Ga)Se₂ Thin Films: An Innovative Al₂O₃/HfO₂ Multistack Design

15.3: Defect Engineering in n‐Type Oxide Semiconductor TFTs

Wafer‐Scale Nanoimprint Lithography Process Towards Complementary Silicon Nanowire Field‐Effect Transistors for Biosensor Applications

Surface Passivation of CIGS Solar Cells Using Gallium Oxide

A Robust 10-Gb/s Duobinary Transceiver in 0.13-μm SOI CMOS for Short-Haul Optical Networks

Intrinsic rectification in common-gated graphene field-effect transistors

Leakage Current and Low-Frequency Noise Analysis and Reduction in a Suspended SOI Lateral p-i-n Diode

An 80-MHz 0.4V ULV SRAM macro in 28nm FDSOI achieving 28-fJ/bit access energy with a ULP bitcell and on-chip adaptive back bias generation

Multiple-Wavelength Detection in SOI Lateral PIN Diodes With Backside Reflectors

Experimental evaluation of mismatching on the analog characteristics of GC SOI MOSFETs

Comparative experimental study of the improved MOSFETs matching by using the hexagonal layout style

A Quasi-Static Model of Silicon Substrate Effects in Graphene Field Effect Transistors

Automated layout-integrated sizing of a 2.45 GHz differential-drive rectifier in 28 nm FDSOI CMOS

Optimisation of rear reflectance in ultra-thin CIGS solar cells towards >20% efficiency

Quantum Efficiency Improvement of SOI p-i-n Lateral Diodes Operating as UV Detectors at High Temperatures

Boosting the SOI MOSFET Electrical Performance by Using the Octagonal Layout Style in High Temperature Environment

Efficient passive energy harvesters at 950 MHz and 2.45 GHz for 100 μW applications in 65 nm CMOS

Low power highly linear temperature sensor based on SOI lateral PIN diodes

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