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We developed a 4Mb split-gate e-flash on 28-nm low-power HKMG logic process, which demonstrates the smallest bit-cell size (0.03×-um2) for high performance IoT applications. High speed operation (25us write time and 2ms erase operation) and robust reliability (500K cycle, 10 years retention) are achieved through optimization of triple-gate flash architecture and scaling of word-line (WL) transistor...
A publisher/subscriber model dominates today's Internet usage behavior instead of a location-based host access. Along with this stream, Information-Centric Network (ICN) is proposed for Future Internet Architecture to remedy the problems the current Internet is encountered. Although there are lots of research efforts on ICN, but still evaluation and validation of their proposals stay at simulation...
While the current Internet has a host-based TCP/IP architecture, the vast majority of Internet usage is attributed to the content retrieval and distribution. This mismatch has proliferated content delivery network (CDN) technologies and P2P file-sharing systems (e.g., BitTorrent); however, the inefficiency of content delivery is not fundamentally solved, and there are business/operation and content...
In this paper, a heterogeneous 3D-media processor is presented, which supports all 3-D display applications by combining a 3-D display IP with a 3-D graphics IP and a stereo video decoder. For mobile environments, adaptive power management scheme is proposed, which saves power consumption up to 186 mW by turning off idle functional blocks based on a target application, a target performance, and the...
A mobile heterogeneous 3D-media processor which supports all 3D display contents by combining a 3D display IP with a stereo video decoder and a 3D graphics IP is proposed. For mobile environment, adaptive power management scheme is adopted, saving 165mW. For high-end applications, fast modulo operators are designed to synthesize 3D images at 116fps, 17 times faster than the previous work. An IEEE...
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