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24-GHz band amplifiers with a high image-rejection function have been designed and characterized using a 0.18-??m SiGe BiCMOS technology. To achieve a higher image-rejection ratio (IRR) in the quasi-millimeter-wave frequency region, an amplifier configuration with a notch-filter type feedback circuit has been proposed. A low noise amplifier (LNA) and a driver amplifier (DA) were developed to eliminate...
An image-rejection low-noise amplifier (LNA) based on 0.18-mum SiGe BiCMOS technology was developed in order to create a 24 GHz-band RF receiver front-end. Its high image-rejection ratio (IRR) in the quasi-millimeter-wave frequency region is due to the use of a notch feedback circuit. The LNA has a 14-dB gain at an operating frequency of 27.2 GHz and an IRR greater than 50 dB IRR at an image frequency...
In this work, a 59 GHz push-push VCO is based on a new output circuit concept to simultaneously achieve both wide tuning range and high output power. It achieves a wide frequency tuning range of 13.9 GHz, high output power of 1.2 dBm, and low phase noise of-108 dBc/Hzat 1 MHz offset frequency. To the authors' knowledge, its figure of merit (FOMT) of -189.6 dB is the best for silicon-based 50 GHz class...
We propose a digital output piezoelectric accelerometer for chicken health monitoring. The accelerometer has patterned Pb(Zr, Ti)O3 (PZT) thin films electrically acc connected in series, which accompany CMOS switches. The elerometer converts acceleration into number of on-state CMOS switches, which can be called as "digital output". Since the accelerometer are based on piezoelectric effect,...
We have developed a novel piezoelectric accelerometer with digital output for ultra-low power wireless sensor nodes. The accelerometer is composed of an array of piezoelectric parallel-plate capacitor structures that are joined together in series and connected to a CMOS switch array. This composition makes it possible to realize a digital output accelerometer in which the number of on-state CMOS switches...
A full-rate 10 Gb/s transceiver core employing a tri-state binary PD with 100ps gated digital output is implemented in a 90nm CMOS process. Direct drive from the VCO is utilized to eliminate the 10GHz clock buffer current. The RX exhibits a recovered-clock jitter of 906fsrms and an input sensitivity of 5.9mVpp. The TX generates a jitter of 5mUIrms. The chip consumes 250mW.
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