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In the nano-scaled technologies, increasing sub-threshold leakage, dynamic power and degrading SNM pose major hurdle for future generation circuits, especially in SRAM arrays. In this paper, a novel high write speed, low power, read-SNM-free 6T SRAM cell is presented. Simulation using 128 times 16 SRAM array in 90 nm CMOS technology shows that the cell can achieve 64% faster write operation than the...
With reducing feature sizes, SRAM stability has become a major concern for future technologies. This critical issue can be solved by using highly stable separate bit-line read SRAM cell, but access time improvement becomes critical, since differential sense amplifier cannot be used for single bit-line read operation. In this paper, a novel pseudo differential single ended current mode sense amplifier...
As the MOSFET's channel length is scaling down, SRAM stability becomes the major concern for future technology. The cell becomes more susceptible to both process induced variation in device geometry and threshold voltage variability due to dopant fluctuation in the channel region. In this paper, a novel highly stable 8T SRAM cell is proposed which eliminate any noise induction during read operation...
As the MOSFETs channel length is scaling down, SRAM stability becomes the major concern for future technology. The cell becomes more susceptible to both process induced variation in device geometry and threshold voltage variability due to dopant fluctuation in the channel region. In this paper , a novel highly stable 8T SRAM cell is proposed which eliminates any noise induction during read operation...
Inter-die and intra-die variation in process parameters increases parametric failures and leakage spread in nano-scale memories, leading to significant yield degradation. Design level optimization methods are not sufficient to address the leakage and parametric failures, particularly, under large variation. In this paper, we propose two post-silicon tuning techniques which can simultaneously reduce...
Increasing source voltage (source-biasing) is an efficient technique for reducing gate and sub-threshold leakage of SRAM arrays. However, due to process variation, a higher source voltage can significantly increase data flipping in standby mode (hold failures) resulting in faulty memories. This imposes serious concerns in reducing standby power with source-bias. In this paper, we analyze the effect...
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