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This paper presents a novel power and reliability-aware task mapping approach in many-core platforms for hard realtime applications which is called LORAP. The LORAP contrives a task mapping scenario to meet the predefined reliability threshold ensuring minimum power consumption overhead. It drastically decreases task mapping time complexity and uses slack time of running applications to apply a heuristic...
In Networks-on-chip, increasing the depth of routers' buffers even by a few stages can have a significant effect on average latency and saturation threshold of the network. However, the price to pay could be high in terms of power and silicon area. In this paper, we propose a low power, high throughput asynchronous FIFO suitable for buffers of GALS NoC routers. We consistently compare the performance...
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