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In this paper, a PVT Insensitive Time to Digital Converter is proposed to provide a stable reference clock signal of a phase-locked loop. The time resolution can be independent on process, voltage, and temperature variations. In order to produce 16-phase signals, eight series of differential delay elements are utilized. Then, interpolated architecture is used to increase the reference frequency such...
This paper presents a low temperature coefficient BiCMOS voltage reference circuit designed in IBM's 8HP Silicon-Germanium (SiGe) technology platform. A BiCMOS compensation approach by combining the temperature properties of HBTs and CMOS transistors has been employed: the Complementary to Absolute Temperature (CTAT) current is generated by a SiGe HBT, while the Proportional to Absolute Temperature...
This paper presents a wide-band low-power super-heterodyne RF front-end for the Medical Implant Communications Services (MICS) band. The front-end consists of a low-noise amplifier (LNA), a mixer, buffers, and passive baluns. The proposed circuits feature the techniques of current-reuse, MOSFET back-gate coupling, feedback, and current bleeding to achieve low power under acceptable noise figure (NF)...
In this paper, a CMOS CO2 concentration to frequency converter with calibration circuits is newly proposed. A calibration technique is proposed in this work. Another innovation is that the outputs of the proposed chip are directly digitized, they could be easily sent over a wide range of transmission media, such as PSN, radio, optical, IR, ultrasonic, and etc. Before performing the proposed calibration...
This work presents a column level binning circuit for a CMOS image sensor for detecting low-light imaging. A 2×2 kernel pixel binning (averaging) is employed in this design reducing the spatial resolution to 1/4 of the original size and every two columns of the pixel array share one binning circuit. The output signal of each pixel is sampled unto the binning circuit basically composed of two adjacent...
In this paper, the power gain improvements by stress contact etch stop layer (CESL) in a 65-nm nMOSFET were studied. Compared to the conventional nMOSFET, the device with CESL stress shows an extra 6% power gain enhancement for the increased stress in the channel region. This study also presents the polyharmonic distortion (PHD) model extraction by X-parameters measurement when the power transistor...
A miniaturized and low-insertion-loss V-band bandpass filter implemented on the integrated passive device (IPD) is demonstrated. The architecture is composed of two quarter-wavelength transmission lines with vias, which form the two spiral-type resonators. Then, aperture compensation technique is applied to enhance the coupling between two resonators. The filter exhibits low insertion loss around...
A novel system on package (SoP) RF frontend module for X-band frequency modulated continuous wave (FMCW) sensor is presented in this paper for short distance moving object detection. A multifunction RFIC chip realized by typical 1P6M 0.18 ??m deep n-well CMOS technology, a multilayer 180?? hybrid and two embedded ring filters, two sets of antenna arrays, and all other necessary components are all...
A CMOS analog front-end (AFE) circuit for portable biomedical signals acquisition system is presented in this paper. A low-power instrumentation amplifier (IA) is chosen as an AFE circuit for portable biomedical application using simplified differential difference amplifier (DDA). The presented IA is designed in standard 0.18 mum 1P6M CMOS process technology at a 1.8-V supply voltage. The simulation...
This paper reviews the measurement and modeling issues of the channel thermal noise in MOSFETs as a result of the aggressive reduction of the channel length into the sub-100 nm regimes. It also shows the noise performance of devices in 65 nm CMOS technology.
A 2.4 GHz linear CMOS power amplifier (PA) for OFDM WLAN application in 65 nm CMOS technology is presented. The cascode PA operating from 3.3 V employs the proposed asymmetric lightly doped drain MOSFET (A-LDD) structure as common-gate stage to sustain large signal stress and 1.2 V core device as common source stage to provide high frequency operation. Beside, dynamic bias technique is used not only...
This work presents a new architecture of spread-spectrum clock generator providing 1.5-Gbit/s, 3-Gbit/s and 6-Gibt/s SATA compatible specifications. A two-stage delta-sigma modulator is proposed to simplify the hardware and to overcome the nonlinearity issue of triangular control voltage induced by supply voltage, process and temperature variations. The peak energy of the output clock spectrum is...
This work presents an all digital time to digital converter (TDC) utilizing two-step Vernier delay chain. The sampling phases are generated using a single delay-locked loop (DLL). The design includes an adjustable resolution for obtaining small area and low power dissipation and can be applied as a high resolution frequency to digital converter and jitter measurement system. The design has an adaptive...
In this work, the CMOS bulk-input current switch logic (BCSL) circuit is proposed. A negative (positive) boost circuit providing a voltage level for NMOS (PMOS) bulk terminal is also developed to avoid the forward biasing of drain/source-to-bulk junctions. A current latch sense amplifier is used to generate a pair of full-swing output signals without dc power dissipation. The devices in the differential...
This work presents a current-mode differential bidirectional transceiver with adaptive impedance matching architecture. The current signals are transmitted bidirectionally on a shared interconnection to double up the data rate. The voltage swing on the wire is reduced so that the proposed scheme consumes less power at higher data rate. The proposed adaptive impedance matching circuit has the ability...
A low-voltage low-power bandgap voltage reference without using passive components is presented. Using piecewise linear curvature-compensated scheme, a reference voltage of 646.4 mV is generated with a temperature coefficient of 1.7 ppm/degC in the range [-40, +125] degC at 1.8-V supply voltage. A line sensitivity of 0.18 mV/V in the supply voltage range [+1, +1.8] V is achieved. It dissipates a maximum...
This paper proposes a cost-effective RF power cell manufactured in an advanced 0.13 um CMOS technology. Without adding additional masks, cost, and process, the power performance can be improved just by using the standard N-well and shallow-trench-isolation processes to form a higher resistive region. This ldquoPseudo-Drainrdquo structure increases the breakdown voltage to more than 4.3V and is higher...
A low-power transceiver for 802.11n in 65 nm CMOS technology is presented. It supports 2times2 MIMO to satisfy the requirement of the draft 802.11n standard. In receiver chain it shows 5.3 dB low noise figure. In transmit chain an on-chip PA driver delivers 9 dBm output P1dB. -20 to 100degC operation temperature is achieved. A SigmaDelta fractional-N synthesizer is used to support variable reference...
A fully integrated 2.4/5.2-GHz dual-band low-noise amplifier (LNA) / mixer for implantable biotelemetry is presented. By using conjugate matching technique, the proposed front-end receiver circuit integrates LNA output and mixer input into a single chip at the 2.4 GHz and 5.2 GHz ISM band. The proposed front-end circuit was designed for super-heterodyne receiver. By switching local oscillator (LO)...
This work presents a low-power 50% duty cycle corrector. A single-ended structure is adopted. The gain-boosting charge pump raises the loop performance and decreases the voltage ripples for increasing accuracy. The input duty range and operational frequency range are increased. The parameters of the design are optimized by loop analysis. A test chip is implemented in a 0.18 mum CMOS process. It's...
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