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In this talk we will discuss fabrication and device aspects of IBMs work on III–V Tunnel FETs. Since our focus is on the monolithic integration of III–V on Si, we will show our recently developed Template Assisted Selective Epitaxy (TASE) technology and its application to both TFETs as well as other electronic devices. In TASE, III–V materials can be grown within templates, which allows for versatility...
This paper presents a simulation study of In0.53Ga0.47As/InP heterojunction gate-overlapped-source tunnel FETs (GoS-TFETs) with pocket counter-doping. The effect of channel quantization on the line tunneling is considered in the semiclassical simulations using a new model that modifies the band edge in the inversion layer. The small bandgap of the source material In0.53Ga0.47As results in an improved...
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