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The last decade has seen an explosion in research efforts which attempt to miniaturize rack-mounted, neural interface electronics to a form that is easily implantable for in vivo applications. Commensurate with this trend, neural scientist and engineers are demanding higher performance electronics for neural stimulation, recording, encoding, communication and energy harvesting, all in the context...
Presents the introductory welcome message from the conference proceedings. May include the conference officers' congratulations to all involved with the conference event and publication of the proceedings record.
Rumors of Moore's Law demise have been greatly exaggerated! While transistors are not getting simultaneously smaller, faster and lower power every couple of years like for the past several decades, inexorable forces to cram more devices together are still running strong, except that they are now pushing upwards in the third dimension. Heterogeneity, monolithic vs. TSV-based scaling for 3D, and closing...
For almost 30 years, the IEEE International System-on-Chip Conference (SOCC) has been the premier forum for sharing advances in system-on-chip (SoC) technologies, designs, tools, test and verification. The SOC conference rotates amongst international locations, and attracts researchers and engineers from all over the world to exchange knowledge, share experiences and establish collaborations with...
The Internet of Things is creeping into ever more critical areas of our lives. From drug pumps to aircraft, connected cars and even smart weapons - there are few products coming off the production line today which don't have an added element of ‘intelligence’ and connectivity. There's just one problem: they are fundamentally flawed. And in this brave new world, that could result not just in data theft...
This talk presents some of the prominent barriers to designing energy-efficient circuits in the sub-14nm CMOS technology regime and outlines new paradigm shifts necessary in next-generation multi-core microprocessors and systems-on-chip. Emerging trends and key challenges in sub-14nm design are outlined, including (i) device and on-chip interconnect technology projections, (ii) performance, leakage...
Cyber-physical systems are engineered systems that require tight conjoining of and coordination between the computational (discrete) and the physical (continuous). Cyber-physical systems are rapidly penetrating every aspect of our lives, with potential impact on sectors critical to national security and competitiveness, including aerospace, automotive, chemical production, civil infrastructure, energy,...
Cyber-physical systems are integrations of computation, communication networks, and physical dynamics. Applications include manufacturing, transportation, energy production and distribution, biomedical, smart buildings, and military systems, to name a few. Increasingly, today, such systems leverage Internet technology, despite a significant mismatch in technical objectives. A major challenge today...
Due to high latency and high power consumption in long hops between operational cores of Network-on-Chips (NoCs), the performance of such architectures has been limited. Billions of transistors available on a single chip present opportunities for new levels of computing capability. In order to fill the gap between computing requirements and efficient communications, a new technology called Wireless...
Wireless NoC is becoming popular to be a promising future on-chip interconnection network as a result of high bandwidth, low latency and flexible topology configurations provided by this emerging technology. Nonetheless, congestion occurrence in wireless routers negatively affects the usability of high speed wireless links and considerably increases the network latency, therefore, in this paper, a...
Wireless NoC is becoming popular to be a promising future on-chip interconnection network as a result of high bandwidth, low latency and flexible topology configurations provided by this emerging technology. Nonetheless, congestion occurrence in wireless routers negatively affects the usability of high speed wireless links and considerably increases the network latency, therefore, in this paper, a...
Because of high bandwidth, low latency and flexible topology configurations provided by wireless NoC, this emerging technology is gaining momentum to be a promising future on-chip interconnection paradigm. However, congestion occurrence in wireless routers reduces the benefit of high speed wireless links and significantly increases the network latency, therefore, in this paper, a Dynamic Application...
On behalf of the Technical Program Committee, we welcome you to the 27th IEEE International System-on-Chip Conference, held this year in Las Vegas, Nevada. For over 25 years, SOCC including its predecessor conferences ASIC and ASIC/SOC has been one of the premier conferences for sharing advances in SoC technologies and applications. This year we continue this tradition with an outstanding technical...
This paper presents a novel design method for power-aware test wrappers targeting embedded cores with multiple clock domains. We show that effective partitioning of clock domains combined with bandwidth conversion and gated-clocks would yield shorter test times due to greater flexibility when determining optimal test schedules especially under tight power constraints.
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