The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
This paper describes a systematic approach to design FPGA package for current carrying capability. As we examine silicon, interposer, and package, the profound challenge is found to meet the lifetime of high power device against the greater chance of failures owing to worsen electro-migration in every interconnect level. Our approach consists of practical methodologies to estimate current distribution...
Jitter margin loss as result of crosstalk impairment emerges as increasing challenge at 28Gbps and beyond. As silicon compensation is known ineffective to crosstalk, package becomes critical path of system jitter margin. At this speed, signal coupling needs to be kept at well below -50dB in order to ensure adequate insertion-loss-to-coupling ratio (ICR) for protocol jitter compliance. In this paper,...
The recent market demand to high power 16nm FPGA has challenged package design to an unprecedented level. Specifically, logic tense applications require significantly greater dynamic current than previous generations. This paper describes recent advancements in high power FPGA package design for current-carrying capability. Firstly, new design methodologies are introduced that can link physical design...
The applications to increasing number of transceivers and data rate require extra ground pins (i.e. BGA balls) reserved for channel isolation and crosstalk control. To improve total pin utilization, a transceiver package often resorts to power pins to replace up to 50% of ground pins. However, power pins can fail providing adequate isolation for transceivers operating at 16Gbps and higher data rate...
As the FPGA device performance increases and integrated circuit reduces in size there will be more and more challenges on the package design. Detailed analysis to capture and address design challenges is important for a viable power distribution network (PDN) package design. This paper will discuss the modeling methodology to analyze the static voltage drop for the high performance and high density...
With silicon process technology advanced to 20 nm node and beyond, die size is continuously shrinking. Package cost is very sensitive to the total cost of an entire chip/ASIC (Application-Specific Integrated Circuit). To reduce package cost, either the package layer count needs to be reduced or the package size needs to be decreased. For a given chip/ASIC design, its high-speed IO (Input Output) pin...
Wire bond packaging for semiconductor devices has been the choice of low cost implementation to memory interface and high-speed transceivers. However, accurate characterization for wire bond package remains challenging owing to lack of consistent probing methodology. Meanwhile, semiconductor devices tend to have increasingly higher density of I/O, logic circuits and transceiver circuits yet shrinking...
This paper presents a crosstalk model base on even-odd mode analysis. It demonstrates that crosstalk analysis needs to look at the aspect of the timing delay between even and odd mode and the multiple reflections that occurred in a system. This concept is validated further by measurement result.
This paper presents the dominant contributors of mutual inductance in wire-bond package thru study on the return path. The study is validated through real device measurement correlation. Based on the study, techniques to reduce crosstalk in wire-bond package will be presented which will be beneficial to the packaging world as bond wire continues to be the dominant technique to connect die to the package...
This paper presents the dominant contributors of mutual inductance in wirebond package thru study on the return path. The study is validated through real device measurement correlation. Based on the study, techniques to reduce crosstalk in wire-bond package will be presented which will be beneficial to the packaging world as bond wire continues to be the dominant technique to connect die to the package...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.