The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Wafer bumping and flip chip bonding are gaining momentum in the semiconductor packaging arena with the increase in pin count, smaller pad pitch and electrical performance. The cost of wafer bumping and flip chip bonding always hinder the growth for adoption. This paper introduces a patented wafer bumping process known as Double Resist Imaging Process (DRIP) which enables electrolytic wafer bumping...
Flip Chip (FC) interconnects for 3D, 2.5D and wafer level packaging (WLP) are fast becoming a common package for high performance applications. One of key challenges identify in assembly lie in the fine pitch of FC interconnect to the substrate. This paper looks into an instantaneous fluxless bonding techniques of solid liquid interdiffusion by compressive force (SLICF) to form FC joints of Au, Cu,...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.