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We report TaCx/HfSiON gate stack CMOS device with simplified gate 1st process from the viewpoints of fixed charge generation and its impact on the device performance. Moderate Metal Gate / High-K dielectric (MG/HK) interface reaction is found to be a dominant factor to improve device performance. By optimizing TaCx composition, fixed charge free TaCx/HfSiON device is successfully fabricated. Also,...
At the time of CMOS device development in 45 nm node, newly developed materials and techniques have been discussed and experimented to achieve power-performance requirement. Based on the published reports, the overview of current 45 nm node technology development status is summarized. Then, the prevision of 32 nm node device design strategy is discussed considering key technologies such as stress...
We propose sub-1-A-resolution analysis of gate surface layer In scaled-Tinv (capacitance equivalent thickness at substrate inversion) gate stacks by differentiating their C-V curves. By introducing the universal derivative-of-capacitance curve, gate stacks with different equivalent oxide thickness of gate insulator and substrate-impurity concentration JVSub can be analyzed in one and the same plot...
We propose sub-1Aring-order analysis of gate/insulator interfacial region in scaled-Tinv gate stacks by differentiating their C-V curves. By applying this technique to p+ poly-Si/HfSiON, it is found that gate depletion increases due to both lower poly impurity cone. (Npoly) and huge amount of pinning charge inside the dielectric (Nox). We found ultra-thin SiN cap insertion recovers the degradation...
Ge diffusion into high-k layer is completely suppressed by taking advantage of thermally stable Zr-silicate/Ge structure. This leads to high muh of 210 cm 2/Vsec at 0.1M V/cm, which is two times higher than that of ZrO2/Ge and even 23% higher than the value for Si universal curve. EOT scalability of Zr-silicate/Ge gate stacks is comparable to that of ZrO2/Ge one
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