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This paper presents an all-digital phase-locked loop (ADPLL) in the 0.18 pm CMOS process, which uses a multi-stage time-to-digital converter (TDC) with calibration and interpolation digitally-controlled-oscillator (IDCO). The ADPLL also utilizes a frequency tracking engine (FTE) to reduce the system locking time. The ADPLL has a frequency range of 149–1450 MHz, the minimum peak-to-peak jitter achieves...