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In this paper, a bone-guided cochlear implant (BGCI) SOC microsystem is proposed and designed. The BGCI microsystem uses four or more electrodes placed on the bone surface of the cochlea and one on the round window to preserve partially the acoustic hearing. The external SOC of the BGCI processes the acoustic signals and generates stimulation patterns and command that are transmitted to the implanted...
A CMOS Gm-C filter based on operational trans-conductance amplifiers (OTAs) with low power and tuning ability for biomedical applications is proposed in this paper. The OTA works in the weak inversion region. The transconductance can be tuned by changing the bias current. A fourth-order Butterworth LC ladder Gm-C bandpass filter is implemented by 0.18 μm CMOS process. The supply voltage of the OTA-C...
This paper presents an all-digital phase-locked loop (ADPLL) in the 0.18 pm CMOS process, which uses a multi-stage time-to-digital converter (TDC) with calibration and interpolation digitally-controlled-oscillator (IDCO). The ADPLL also utilizes a frequency tracking engine (FTE) to reduce the system locking time. The ADPLL has a frequency range of 149–1450 MHz, the minimum peak-to-peak jitter achieves...
A current-mode dual-slope CMOS temperature sensor is presented in this paper. It employs a proportional-to-absolute-temperature (PTAT) current generator, which operates in the sub-threshold region, and a novel temperature-insensitive CMOS inverter, replacing a traditional voltage comparator for power saving, to create PTAT pulsewidth. A binary counter is then utilized to quantize the pulse to a digital...
A 4-bit continuous-time delta-sigma modulator (CT-DSM) with the proposed data-weighted averaging (DWA) algorithm for audio application is presented. The proposed method randomly adds one to pointer address in the DWA to reduce distortion tones and improve the performance of spurious-free dynamic range (SFDR) and signal to noise and distortion ratio (SNDR), as compared with the conventional DWA. The...
This paper proposes a new architecture of 12-bit current-steering digital-to-analog converter (DAC) with novel biasing scheme. In the proposed DAC, two 6-bit binary-weighted current source arrays are designed with two reference currents. The technique allows significant area savings without impairing static accuracy. The paper also presents a method to generate dual reference currents, whose design...
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