The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
In this study, a stacked SRAM module with a built-in decoder was proposed with a through-multilayer TSV integration process. The through-multilayer TSVs provided data passages for all common signals, including the address bus, data bus, power, read and write control, which were redistributed at each individual chip, while the chip select signals were connected separately to the built-in decoder. Regarding...
Metallic wafer bonding has emerged as a key technology for microelectronics and MEMS. The Si wafers with Al metallization film on surface are bonded by applying Sn film as intermediate layer, aiming at the application of heterogeneous integration. Averaged shear strength of 9.9 MPa is realized at bonding temperature as low as 280°C with bonding time as short as 3 minutes under the bonding pressure...
In this paper, a through-stack-via integration process for SRAM module was developed using wafer level pre-patterned BCB bonding. A SRAM module with a built-in decoder has been designed according to this integration process. TSVs passed through all stacked SRAM chips and common signals, including address bus, data bus, power, write and read control, were connected to the same TSV using RDL. The chip...
3D integration with TSVs (Through Silicon Via) is emerging as a promising technology for the next generation integrated circuits. Copper electroplating is one of the key technologies to fabricate TSVs. In this paper, void-free TSV filling was achieved using methanesulfonic based electrolyte and mushroom-like copper overburden was used as bumps after tin deposition. Effect of additives and current...
In this paper, a TSV last wafer level 3D integration scheme using pre-patterned benzocyclobutene (BCB) adhesive bonding was proposed. With pre-patterned BCB adhesive bonding, a one-time bottom-up TSV filling features as the last step, which eliminates the traditional solder bumping and underfill filling. Preliminary results show that this process is promising for integration of similar chips such...
Redistribution layer (RDL) is necessary for electric interconnection of TSV-based 3D stacking applications. Fabrication process and electrical measurement of RDL using benzocyclobutene(BCB) as interlayer dielectric is investigated in this paper. Photosensitive BCB and electroplating copper are applied in this process featured with low temperature below 250. Multilayered RDL has been fabricated by...
In this paper, a novel 3D integration process named Via-Backside-Release process, abbreviated as VBR process, is proposed and technical issues are addressed. With VBR process, there's no need of removal process of copper overburden due to the filling of TSV by copper electroplating, and no individual unit process for producing Cu/Sn microbumps. In order to verify the feasibility of VBR process, a...
Tapered TSV interconnection has begun used in CMOS Image Senor (CIS) and currently is penetrating its application in other areas, such as MEMS devices and Si Interposer. It helps relive the technical difficulties of conformal deposition of insulation layer and conducting layer and therefore it's helpful for yield improvement and cost reduction. Besides that, it helps also relieve the stress accumulation...
Tungsten is a promising bulk material for microsystem applications for its high melting point, radiation resistance, high strength and conductivity. In this paper, wafer level Tungsten-Glass wafer bonding was carried out with photodefinable BCB, the results were compared with Si-Glass bonding. A high-yield BCB bonding technology was developed with good uniformity and relatively high bonding strength,...
3D System in Package with Through Silicon Via has been a promising solution to enhance the integrated density[1]. However, as more and more devices are integrated in one package, the reliability and performance is affected by the work environment, such as temperature variation, vibration, drop and so on. Many researches has been done on the drop analysis of solder ball on the PCB substrate, but few...
3D integration with TSVs is emerging as a promising technology for the next generation integrated circuits. TSV filling is a critical process in TSV fabrication and has direct effect on electrical performance of TSVs. In this paper, we mainly focus on effect of additives used in methanesulfonic based solution on copper electroplating filling. Numerical simulation based on an absorption-diffusion model...
In this paper, a stacked SRAM chip module is presented and simulation results are demonstrated. A novel 3D integration process is presented and challenging issues are addressed. With this novel process, there's no need to do grinding/polishing of copper overburden after filling of TSV by copper electroplating. Copper microbumps will be formed directly on the active side in the filling of TSV by copper...
In this paper, electrical characteristic of TSV (Through Silicon Via) is analyzed. Firstly, equivalent circuit model of TSV is summarized. Modeling and electrical analysis of TSV is conducted, in which TSVs with ideal and non-ideal profiles are compared. And then, multi-TSV configuration in silicon interposer is modeled and analyzed. Capacitive and inductive coupling between TSVs are simulated. With...
In this paper, a monolithic integration structure with TSV interconnections is introduced for un-cooled infrared FPA to do easy wafer-level-package. Firstly, the challenging process for making the structure will be reviewed and identified. And then process sequence for making the TSV interconnections and RDLs and CMOS compatible surface process for IR FPA will be developed. In the end, a WLP scheme...
In this paper, the potential application of combining cylindrical TSV and annular TSV into 3D integration was studied. First, the schematic fabrication process of cylindrical and annular TSV was proposed. Lumped equivalent circuit model of these different kinds of TSV structures from the physical configuration were studied and verified. Besides, 3D full wave electromagnetic (EM) simulations of cylindrical...
TSV interposer provides a cost efficient solution way for 3D IC integration. In this paper, a TSV interposer technology is proposed for SRAM stacking. A simple fabrication process is developed for cost-sensitive application. The mushroomlike Cu/Sn bumps by copper overburden can be directly connected with other substrate, which eliminates a CMP planarization to improve the yield and reduce fabrication...
In this paper, a process for making copper Though-Silicon-Via (TSV) interconnection is developed. In order to improve the yield of the process, challenging issues in the process is discussed and typical failures in the TSV interconnection are summarized. A measuring scheme is proposed to monitor these failures in the process and simulation is performed to testify the feasibility of the method.
As multiple layers of planar device are stacked to alleviate signal delay problem and reduce chip area, Through silicon via (TSV) is introduced to replace the large number of long interconnects needed in previous 2D structure. However, the thermal-mechanical reliability problems of TSVs, such as interfacial delamination, via cracking and so on, have become a serious reliability concern. In this paper,...
The fabrication of redistribution layer (RDL) for TSV 3D integration and its optimization are presented in this paper. BCB is selected as the passivation layer and the electroplated Cu is used as the metal layer. CYCLOTENE 3024–46 is utilized and it is deposited by spin-coating and soft cure at 210 °C in annealing oven for 40 minutes with N2 protection. Sputtered Ti/W/Cu and electron beam evaporated...
In this paper, at first electroplating of copper and tin is optimized to fabricate micro-bump. Chip-to-chip bonding process is developed. Then, a temporary bonding process is developed and verified by experiment. And finally, a process for manufacturing multiple layer stacked chip module is designed and prototype of a 4 layer stacked chip module is fabricated successfully.
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.