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In a multi-core environment with several applications executing in parallel, system performance is significantly impacted by network and memory performance. The manner in which network packets and off-chip memory bound packets are handled determines end-to-end latencies across the network and memory. Several techniques have been proposed in the past that schedule packets in an application-aware manner...
In contemporary semiconductor technologies, considerable unpredictability in the behavior of manufactured chips is being observed due to the effects of process variations. This unpredictability translates into variations in power and performance within these chips. At the same time, with ever shrinking power budgets and rising cooling costs, most chip designs need to satisfy a hard limit on the maximum...
In this paper, we focus on power and thermal management for multicore embedded systems with solar energy harvesting as the power source and a periodic hard real-time task set as the workload. We design a novel semi-dynamic scheme, which reschedules tasks at the beginning of specified time epochs. By rejecting job instances of certain tasks until the next rescheduling point, our scheduler dispatches...
A stable voltage supply is critical for multiprocessor system-on-chips (MPSoCs) to operate at near-optimal performance levels. The problem of IR drops in a Power Delivery Network (PDN) is very severe in 3D MPSoCs with network-on-chip (NoC) fabrics where the current in the PDN increases proportionally with the number of device layers. At the same time, with the increasing core counts in today's power-hungry...
With feature sizes far below the wavelength of light, variations in fabrication processes are becoming more common and can lead to unpredictable behavior in modern multiprocessor system-on-chip (MPSoC) designs. The design costs associated with margining required to overcome this unpredictability can be prohibitively high. System-level design approaches that are aware of these variations can be crucial...
In sub-65nm CMOS process technologies, networks-on-chip (NoC) are increasingly susceptible to transient faults (i.e., soft errors). To achieve fault tolerance, Triple Modular Redundancy (TMR) and Hamming Error Correction Codes (HECC) are often employed by designers to protect buffers used in NoC components. However, these mechanisms to achieve fault resilience introduce power dissipation overheads...
The power consumption of data centers has been increasing at a rapid rate over the past few years. Many of these data centers experience physical limitations on the power needed to run the data center. This paper attempts to maximize the performance of a data center that is subject to total power consumption and thermal constraints. We consider a power model for a data center that includes power consumed...
Hybrid nanophotonic-electric networks-on-chip (NoC) have been recently proposed to overcome the challenges of significant power dissipation and high data transfer latencies in traditional electrical NoCs. However, with increasing embedded application complexity, hardware dependencies, and performance variability, optimizing hybrid nanophotonic-electric NoCs requires traversing a massive design space...
IR drops in a Power Delivery Network (PDN) on chip multi-processors (CMPs) can worsen the quality of voltage supply and thereby affect overall performance. This problem is more severe in 3D CMPs with network-on-chip (NoC) fabrics where the current in the PDN increases proportionally to the number of device layers. Even though the PDN and NoC design goals are non-overlapping, both the optimizations...
With increasing performance-per-watt implementation requirements for emerging applications and barriers in interconnect scaling for ultra-deep sub micron (UDSM) technologies, traditional 2D integrated circuits (2D-ICs) are being pushed to their limit. Three dimensional integrated circuits (3D-ICs) have recently emerged as a promising solution that can overcome many of the performance, area, and power...
Within the past decade, mobile computing has morphed into a principal form of human communication, business, and social interaction. Unfortunately, the energy demands of newer ambient intelligence and collaborative technologies on mobile devices have greatly overwhelmed modern energy storage abilities. This paper proposes several novel techniques that exploit spatiotemporal and device context to predict...
In a heterogeneous environment, uncertainty in system parameters may cause performance features to degrade considerably. It then becomes necessary to design a system that is robust. Robustness can be defined as the degree to which a system can function in the presence of inputs different from those assumed. In this research, we focus on the design of robust static resource allocation heuristics suitable...
In Networks-on-Chip (NoC), with ever-increasing complexity and technology scaling, transient single-event upsets (SEUs) have become a key design challenge. In this work, we extend the concept of architectural vulnerability factor (AVF) from the microprocessor domain and propose a network vulnerability factor (NVF) to characterize the susceptibility of NoC components such as the Network Interface (NI)...
Mobile battery-operated devices are becoming an essential instrument for business, communication, and social interaction. In addition to the demand for an acceptable level of performance and a comprehensive set of features, users often desire extended battery lifetime. In fact, limited battery lifetime is one of the biggest obstacles facing the current utility and future growth of increasingly sophisticated...
Energy-efficient resource allocation within clusters and data centers is important because of the growing cost of energy. We study the problem of energy-constrained dynamic allocation of tasks to a heterogeneous cluster computing environment. Our goal is to complete as many tasks by their individual deadlines and within the system energy constraint as possible given that task execution times are uncertain...
In recent years, the rise in the number of cores being integrated on a single chip has led to a greater emphasis on scalable communication fabrics that can overcome data transfer bottlenecks. Network-on-Chip (NoC) architectures have been gaining widespread acceptance as communication backbones for multi-core systems, due to their high scalability, predictability, and performance. However, NoCs are...
Multiple use-case chip multiprocessor (CMP) applications require adaptive on-chip communication fabrics to cope with changing use-case performance needs. Networks-on-chip (NoC) have recently gained popularity as scalable and adaptive on-chip communication fabrics, but suffer from prohibitive power dissipation. In this paper we propose UC-PHOTON, a novel hybrid photonic NoC communication architecture...
Power is one of the major constraints considered during the design of embedded software. In order to reduce power consumption without sacrificing performance, software needs to be optimized in order to run as efficiently as possible on a given platform. When attempting to optimize the mapping of a piece of software on a multiprocessor system, designers often face the chicken-and-egg problem of whether...
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