The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
This paper presents a novel, energy-efficient DRAM refresh technique called massed refresh that simultaneously leverages bank-level and sub array-level concurrency to reduce the overhead of distributed refresh operations in the Hybrid Memory Cube (HMC). In massed refresh, a bundle of DRAM rows in a refresh operation is composed of two subgroups mapped to two different banks, with the rows of each...
Integrated silicon photonics represents one of the more promising solutions to overcome the challenge of worsening on-chip communication performance in emerging multicore platforms. This paper highlights recent innovations in architectures, protocols, and techniques to enhance performance, dependability, and power-efficiency for integrated photonics.
The proliferation of distributed data centers has recently motivated researchers to study energy cost minimization at the geo-distributed level. Researchers have been using models for time-of-use (TOU) electricity pricing and renewable energy sources to help reduce energy costs when performing geographical workload distribution, but have made oversimplifying assumptions at the data center level. Important...
There has been growing interest in location-based services and indoor localization in recent years. While several smartphone based indoor localization techniques have been proposed, these techniques have many shortcomings related to accuracy and consistency. These prior efforts also ignore energy consumption analysis which is a crucial quality metric in resource-constrained smartphones. In this work,...
This paper presents a high-bandwidth 3D graphics DRAM architecture (3D-SGDRAM) with reduced access time and energy consumption. A novel 3D bank organization is employed with TSVs at subar-ray-level granularity to activate an optimal number of subarrays in lock-step to guarantee fast and low-energy memory access without significant area overhead. A new bitline interface enables access to only a selective...
Crosstalk noise can significantly reduce data transfer reliability in emerging photonic network-on-chip (PNoC) architectures. Undesirable mode coupling between photonic signals at microring resonators (MR) is the main cause of crosstalk in photonic waveguides. As emerging PNoC architectures employ dense wavelength division multiplexing (DWDM) with multiple cascaded MRs, these architectures suffer...
Emerging multicore processors are increasingly power constrained and plagued by design uncertainty due to process variations. This paper proposes a novel framework that enables runtime core selection, thread-to-core mapping, and extended range dynamic voltage frequency scaling (DVFS) operating under near-threshold computing (NTC), nominal, and turbo-boost (TB) conditions. Our framework leverages the...
As multicore processor architectures are now prevalent in server nodes of parallel and distributed computing systems, it has become important to characterize the performance of applications run on these architectures. This study investigates the performance degradation an application experiences from memory interference due to other applications colocated on cores of the same multicore processor....
With deeper technology scaling accompanied by a worsening power-wall, an increasing proportion of chip area on a chip multiprocessor (CMP) is expected to be occupied by dark-silicon. At the same time, design challenges due to process variations and soft-errors in integrated circuits are projected to become even more severe. In this work, we propose a novel framework that leverages the knowledge of...
The rapid increase in power consumption of high performance computing (HPC) systems has led to an increase in the amount of cooling resources required to operate these facilities at a reliable threshold. The cooling systems contribute a large portion of the total power consumption of the facility, thus driving up the costs of providing power to these facilities. In addition, when cores sharing resources...
In emerging 3D-ICs, thermal hotspots and high IR-drops in the power delivery network (PDN) can significantly limit overall system performance. The high core counts required to support parallel embedded applications in these 3D-ICs also notably increases communication energy. As inter-core communication patterns, IR-drop distributions, and 3D thermal profiles all influence system performance and power,...
This paper introduces 3D-Wiz, which is a high bandwidth, low latency, optically interfaced 3D DRAM architecture with fine grained data organization and activation. 3D-Wiz integrates sub-bank level 3D partitioning of the data array to enable fine-grained activation and greater memory parallelism. A novel method of routing the internal memory bus using TSVs and fan-out buffers enables 3D-Wiz to use...
This corresponds to the material in the invited keynote presentation by H. J. Siegel, summarizing the research in [1], [2]. We address the problem of assigning dynamically-arriving tasks to machines in a heterogeneous computing environment. These machines execute a workload composed of different tasks, where the tasks have diverse computational requirements. Each task has a utility function associated...
In this paper, we address the problem of scheduling dynamically-arriving tasks to machines in an oversubscribed heterogeneous computing environment. Each task has a monotonically decreasing utility function associated with it that represents the utility (or value) based on the task's completion time. Our system model is designed based on the environments of interest to the Extreme Scale Systems Center...
Voice is a very compelling natural interface for mobile computing devices. However, mobile operating system speech solutions (e.g., Siri, Google Voice Search) are platform-specific, making their integration within an enterprise environment difficult due to the lack of uniformity in the user experience as well as concerns over privacy and confidentiality. Hybrid apps can overcome these enterprise-specific...
In chip multiprocessor (CMP) systems with multi-application workloads, communication and memory access both play an important role in influencing system performance. Intelligently prioritizing network packets and memory requests can notably improve system throughput. But with increasing workload diversity in CMPs, applying the same request prioritization rules across the chip can lead to sub-optimal...
Hybrid nanophotonic-electric networks-on-chip (NoC) have been recently proposed to overcome the challenges of high data transfer latencies and significant power dissipation in traditional electrical NoCs. But hybrid NoCs with nanophotonic guided waveguides and silicon microring resonator modulators impose many challenges such as high thermal tune up power and crossing losses. Due to these challenges...
In this paper, we propose a hybrid design-time and run-time framework for reliable resource allocation, i.e., mapping and scheduling of applications, in multi-core embedded systems with solar energy harvesting. Our framework is designed to cope with the complexity of an application model with data dependencies and run-time variations in solar radiance, execution time, and transient faults, with support...
In emerging CMOS process technologies, network-on-chip (NoC) fabrics are increasingly becoming susceptible to transient faults. Fault-tolerance mechanisms that are typically employed in NoCs usually entail significant energy overheads that are expected to become prohibitive as fault rates increase in future CMOS technologies. We propose a system-level framework called HEFT to trade-off energy consumption...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.