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As chips increase in complexity with ever increasing power consumption, pressure in efficient power delivery mechanism such as multi-VDD, voltage stacked and DVS continues to rise. The main objective is to reduce the overall current delivered to the chip. For instance, in voltage stacking, if the circuit is stacked in 2 levels and supply voltage is doubled, the current drawn will be reduced by half...
Currently, one of the major bottlenecks in digital design is synthesis. Each iteration of a design takes several hours to synthesize, putting pressure on designers to carefully consider when to submit jobs and wait for the delayed feedback. This delay is especially important in FPGA emulation, when synthesis is performed frequently while fixing the system functionality. This work proposes LiveSynth,...
Pipeline depth and cycle time are fixed early in the chip design process but their impact can only be assessed when the implementation is mostly done and changing them is impractical. Elastic Systems are latency insensitive systems, and allow changes in the pipeline depth late in the design process with little design effort. Nevertheless, they have significant throughput penalty when new stages are...
This paper describes the methodology and algorithms behind extra pipeline analysis tools released in the Xilinx Vivado Design Suite version 2015.3. Extra pipelining is one of the most effective ways to improve performance of FPGA applications. Manual pipelining, however, often requires significant efforts from FPGA designers who need to explore various changes in the RTL and re-run the flow iteratively...
➔ The incremental step of LiveSynth reduces synthesis time by about 95% for incremental changes. ➔ LiveSynth shifts the paradigm to small, incremental changes and more iterations per day. ➔ We advocate for an interactive synthesis flow as a way to boost design productivity.
Current delivery is a major challenge in chip design. Reduction of the nominal voltage due to technology scaling has worsened the problem. Voltage stacking has been proposed as a way to alleviate the problem by delivering power in a serial rather than the conventional parallel way. Several studies have proposed techniques to stack logic designs. This paper applies the voltage stacking technique to...
Conventional cryptosystems collapse in face of attacks mounted with quantum computers, and thus research on quantum cryptography mainly focuses on symmetric cryptography, with which it is impossible to create complete quantum digital signatures. To address these issues, assuming the availability of quantum computers capable of performing Grover search, we explore their constructive influence on post-quantum...
Since the discovery of Shor's algorithm, the anxiety about quantum computation has increased. A large amount of research has been conducted to discover new algorithms and to build a quantum computer. But it seems that a general purpose quantum computer is far from being achieved. Meanwhile, cryptographers around the world started to look for security algorithms that resist to quantum attacks, but...
Complex embedded systems application exhibit time-varying workload which requires continuous resource adaptivity. Workload prediction has been successfully achieved through a hybrid model of NARX Recurrent Neural Networks combined with Self Organizing Map (SOM). This paper presents the performance evaluation of this hybrid time series prediction on embedded processors as an alternative to dedicated...
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