As chips increase in complexity with ever increasing power consumption, pressure in efficient power delivery mechanism such as multi-VDD, voltage stacked and DVS continues to rise. The main objective is to reduce the overall current delivered to the chip. For instance, in voltage stacking, if the circuit is stacked in 2 levels and supply voltage is doubled, the current drawn will be reduced by half. Hence, the same amount of power is delivered, but with half the current. With the prevalence of systems using those techniques, level shifters will have to be optimally designed to perform fast with low power. As the number of level shifters grows, area consumption becomes another design factor. This study explores different types of existing level shifters for voltage stacking application, their optimal sizing and energy, delay and area trade-offs. It includes effect the of PVT variation as another design factor and its impact on delay and energy consumption. We will also propose modifications to the best energy-delay level shifter to reduce its area overhead.