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This paper presents the first detailed analysis of power gating structures in sub-nano scale FinFET circuits. FinFETs are compared with their bulk CMOS counterpart devices to gain design perspective for purposes of power-gating applications. Circuit performance, power, and leakage are analyzed. TCAD device/circuit mixed-mode simulations for a FinFET-based ring oscillator with footer structure are...
This paper shows that by co-designing circuits and systems, considerable power savings are possible if the inherent data redundancy of candidate systems such as wireless is used to compensate for hardware failures. A comprehensive study of 6T SRAM failure modes is presented. The generated statistics are used to quantify a power savings of up to 17.5% for a case study of a 32 nm CMOS 3 GPP WCDMA modem
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