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This paper demonstrates that our very thin film STO capacitor can be located under re-distribution layer (RDL) of WLP/FO-WLP package and is effective for reduction of the power supply noise of LSIs. Their Shmoo plots show improvement of operable frequency and power supply voltage reduction, as results of the improved power integrity realized by our Sub-RDL STO thin film capacitors.
This paper proposes a SPAD array sensor based on breakdown pixel extraction architecture with background readout for scintillation detectors. The proposed architecture extracts the addresses of only the breakdown pixels during the exposure time of the next frame. Therefore, this sensor minimizes the dead time and improve the readout efficiency. A SPAD array sensor was fabricated in a 0.18 μm CMOS...
This paper reports a novel wideband pulse generator implemented in CMOS flipped on a quartz substrate, for low power and low duty cycle applications. The proposed circuit is based on a current-mode excitation as opposed to a typical voltage-mode excitation, allowing the exciter size to be smaller. The new architecture reduces loss from the parasitic capacitance of the excitation circuit, so as to...
Mismatch of power supply integrity between an ATE and a customer board in semiconductor test can lead to test failures such as overkills and underkills. A technique is required to control the power supply impedance of an ATE by feedback control using compensation current injection so that it emulates the impedance of a customer board, eliminating test failures coming from the impedance difference...
The modern VLSI systems that demand high reliability require carefully-designed power/ground network to provide stable power supply. Though the power supply connection is verified before tapeout, it is quite difficult to evaluate its actual quality and reliability after fabrication. This paper proposes a novel way to evaluate the power supply network based on the measurement of magnetic field emission...
A pulse generator (PG) for low power and low duty cycle applications is presented. The PG employs a CMOS switch and a quarter-wavelength transmission line resonator. Since the architecture does not involve feedback gain, the PG is theoretically capable to generate a pulse efficiently at high oscillation frequency (fosc), at which a transistor gain is limited. The PG also features a quick starting...
This paper proposes a breakdown-pixel-extraction architecture for SPAD sensor. The proposed readout circuit detects the breakdown pixels and their addresses are readout. Therefore, under the faint light environment, this SPAD sensor significantly improves the data readout efficiency. A 15 × 15 SPAD sensor was fabricated in a 0.18 um CMOS process, and a high speed readout is verified by measurement.
This paper shows the efficacy of a triangular active charge injection for resonant power supply noise reduction by measuring a real silicon chip. Based on the analysis of a triangular active charge injection, our circuit composed of a voltage drop detector, a finite state machine (FSM) and canceling capacitors injects the adequate amount of charge into the supply line of the LSI so that the core supply...
This paper proposes a fine-time-resolution pulse-shrinking (PS) time-to-digital converter (TDC) based on an offset pulse width detection scheme. The proposed PS TDC detects the end of the conversion utilizing a built-in offset pulse unlike the conventional PS TDCs. Thus it prevents an undesirable non-uniform shrinking rate issue in the conventional ones and contributes to fine-resolution, small-area,...
This paper proposes a new type of power supply circuit for automatic test equipment (ATE) that has ability to emulate arbitrary power supply impedance. It can emulate power supply impedance of customer environment so as to match the power supply voltage fluctuation waveforms of the ATE and of the customer environment, in order to eliminate overkills/underkills coming from the voltage fluctuation difference...
This paper proposes a reference-clock-less burst-mode CDR that resumes from a stand-by state just after a 4-bit preamble utilizing a cycle-lock gated-oscillator based on self-tunable digitally-controlled delay lines. Since the proposed CDR consumes no dynamic power in its stand-by state, it can improve the total power efficiency of serial communication systems that work intermittently such as mobile...
This paper presents a pulse generator (PG), aiming at low power applications with low duty cycle. The PG is capable to provide an efficient pulse generation at a frequency near and beyond CMOS's Fmax. It also features quick starting time and zero stand-by power. The PG is designed by CMOS flipped to a transmission line resonator on a quartz substrate. Efficiency, oscillation frequency and pulse duration...
An optimal design method for a sub-ranging Analog to Digital Converter (ADC) based on stochastic comparator is demonstrated by performing theoretical analysis of random fluctuations in the comparator offset voltage. The proposed performance model is based on a simple but rigorous Probability Density Function (PDF) for the effective resolution of a stochastic comparator. It is possible to approximate...
This paper demonstrates a PLL compiler which generates GDS data from performance specification. Pulse Width controlled PLL (PWPLL) architecture is suitable for a digital-flow PLL design, and there are 8 design parameters in PWPLL, such as the number of stages of the ring oscillator. The inputs for our PLL compiler are standard cell library, SPICE parameters and the target specification file defining...
This paper proposes an analysis of the active charge injection for a resonant power supply noise by controlling the number of canceling capacitors so that the core supply voltage does not become lower than the voltage at the beginning of the canceling charge injection. Based on this analysis, we propose a circuit that injects adequate amount of charge in accordance with the injection time and the...
This paper demonstrates that our Die-Attached STO thin film decoupling capacitor is effective for reduction of the resonant power supply noise of LSIs. Shmoo plots shows improvement of operable frequency and power supply voltage reduction, as results of the improved power integrity realized by our STO thin film capacitors.
This paper presents a time-mode analog signal accumulator that produces two digital signal edges whose time difference is an accumulation of sequence of time difference inputs. Our accumulator holds the time variable by the time interval of two pulses which propagate on a single ring buffers Consisting of even stages of gated inverters, eliminating calibration f drift error due to the delay mismatch...
This paper proposes a method for analyzing the power supply impedance at an on-chip power supply node in the device under test. The proposed method is based on an on-chip power measurement of a power supply voltage fluctuation with sweeping the frequency of the on-chip current load which sinks a square wave current, not sinusoidal. The method can extract the frequency characteristics of not only the...
This paper presents a PWPLL (Pulse-Width Controlled PLL) using a variable-length ring oscillator for autonomously tracking PVT (Process, Voltage and Temperature) variations. We fix the ring oscillator control code and the numbers of the reference CLKs and the feedback CLKs are compared, and then the additional Tracking Circuits switch the number of stages for a PWPLL to be locked. The PWPLL using...
This paper proposes an on-chip measurement method of PLL transfer function. In our proposed scheme, we modulated the phase of the PLL input in triangular form using Digital-to-Time Converter (DTC) and read out the response by Time-to-Digital Converter (TDC). Combination of the DTC and TDC can obtain the transfer function of the PLL both in the amplitude domain and the phase domain. Since the DTC and...
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