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TFET's steep subthreshold slope and asymmetric IDS-VDS characteristics enable energy-efficiency and novel circuits that are not possible with MOSFETs. Logic with low-VDD and memory with low-VMIN are required and possible with TFET. To increase performance despite low-VDD, circuits and logic are re-designed for TFET's unique I–V characteristics. Asymmetric IDS-VDS improves circuit design. Efficiency...
Tunneling FETs (TFETs) offer better low-VDD performance than CMOS but lack performance above 0.5V VDD due to low drive current and VDD-dependent parasitic leakages. At low-VDD, TFET's higher energy efficiency enables 2X parallel performance for power constrained systems. For applications less amenable to parallelization, newly proposed circuits improve energy/op, performance and area by not only using...
Economic viability of on-package, in-situ cooling based on Thin-film Thermoelectric Coolants (TF-TEC) for hot-spot cooling involves myriad challenges necessitating engineering trade-offs. Principal factors include the cost of integration, the net energy consumption of the TEC based system, as well as system-level complexities arising from issues such as mutual thermal conflicts and interdependencies...
For deeply scaled digital integrated systems, the power required for transporting data between memory and logic can exceed the power needed for computation, thereby limiting the efficacy of synthesizing logic and compiling memory independently. Logic-in-Memory (LiM) architectures address this challenge by embedding logic within the memory block to perform basic operations on data locally for specific...
Efficiency and manufacturability of standard cell logic is critical for an IC, as standard cells are at the heart of the nexus between technology definition, circuit design and physical synthesis. Conventional standard cell design techniques are increasingly ineffective as we scale to patterning restricted sub-20 nm CMOS nodes. To meet the constraints and leverage the features of future technology...
Due to escalating manufacturing costs the latest and most advanced semiconductor technologies are often available at off-shore foundries. Utilizing these facilities significantly limits the trustworthiness of the corresponding integrated circuits for mission critical applications. We address this challenge of cost-effective and trustworthy CMOS manufacturing for advanced technologies using split fabrication...
Split fabrication, the process of splitting an IC into an untrusted and trusted tier, facilitates access to the most advanced semiconductor manufacturing capabilities available in the world without requiring disclosure of design intent. While researchers have investigated the security of logic blocks in the context of split fabrication, the security of IP blocks, another key component of an SoC, has...
Split fabrication, the process of splitting an IC into an untrusted and trusted tier, facilitates access to the most advanced semiconductor manufacturing capabilities available in the world without requiring disclosure of design intent. While obfuscation techniques have been proposed to prevent malicious circuit insertion or modifications in the untrusted tier, detecting a pernicious reliability attack...
This paper presents a design methodology forhardware synthesis of application-specific logic-in-memory(LiM) blocks. Logic-in-memory designs tightly integrate specializedcomputation logic with embedded memory, enablingmore localized computation, thus save energy consumption. Asa demonstration, we present an end-to-end design frameworkto automatically synthesize an interpolation based logic-in-memoryblock...
Design rules become ineffective for interfacing layout design and manufacturing when complex lithography sources are used for sub-20nm patterning. Experiments demonstrate feasibility of a construct-based design that facilitates control of process capabilities and captures layout dependent variations. Results for early 14nm patterning experiments are shown for logic and memory circuits.
In this paper we propose a novel architecture with an adaptive approach to the existing partly parallel joint code and decoder design methodology for low density parity check (LDPC) codes. The low power and high throughput are achieved by an 'adaptive iteration controller', regulating the number of iterations required for error correction. We propose an architecture for a 2304 bit, rate-frac12, (3,6)...
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