The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
On the way to full production control, wire bonding equipment requires data-driven condition-based maintenance of the mechanical setup. In this paper, we identify aspects of regular mechanical equipment setups that severely affect bonding quality and equipment health in mass production. We show that mechanical equipment setups lower process stability in aluminum wire bonding. Typical faults in mechanical...
On the way to full production control, wire bonding equipment requires data-driven condition-based maintenance of the mechanical setup. In this paper, we identify aspects of regular mechanical equipment setups that severely affect bonding quality and equipment health in mass production. We show that mechanical equipment setups lower process stability in aluminum wire bonding. Typical faults in mechanical...
Electronic power systems follow the general trend of miniaturization and functional density. 3D technologies provide an interesting response if adapted to power specifications. In the framework of the ENIAC JU funded project Enhanced Power Pilot Line (EPPL), a new type of device has been proposed consisting of an H bridge of power transistors and a Si interposer. This paper presents an H bridge of...
The level of integration for RF and mm-wave systems is continuously increasing. Highly-integrated system on chip solutions have to be encapsulated in a package and assembled on a board. In addition, to be more attractive as a product, the trend goes towards further integration of passives and antennas in a package. This drives the system in package solutions. However, electrical properties of the...
The cost and the package size driven size reduction of semiconductors lead to much higher heat generation. Also the use of new high power technologies on the basis of SiC produces is a need for high conductivity of the interconnect materials. Therefore the requirements for mechanical, thermal and electrical properties of interconnect materials increase compared to existing eutectic solder and glue...
Within this paper, we present a guideline for the mechanical acceleration of reliability experiments for end-of-lifetime prognostics of metal based die attach materials. First, we used an advanced hybrid nano-effect sintered silver layer as interface between die and substrate which has very good electrical and thermal conductivities. Two pairs ofexperiment/simulation are scheduled. An isothermal mechanical...
In this paper, we present the novel embedded Z line (EZL) interconnection technology, which allows fabricating vertical contacts in the embedded wafer level ball grid array (eWLB) package. The presented solution enables the realization of vertical interconnections and passive components of wide range of widths and pitches and high metal-pattern resolution. We discuss the electrical characteristics...
This paper provides an overview of millimeter-wave transceiver frontend concepts and realizations for wireless multi-Gbps communication applications. Different state-of-the-art heterodyne and direct-conversion frontend implementations in silicon-germanium technology (SiGe) with their related applications are presented. These include highly compact embedded transceiver solutions featuring novel antenna-in-package...
Silicon interposers enable the heterogeneous integration of high performance systems. This paper focuses on interconnections from one chip to a neighboring chip in a side-by-side interposer approach. We investigate the performance of interconnections on a typical silicon interposer with polymer applied to the redistribution layer on both sides using electromagnetic simulations. The simulations are...
In this paper we investigate two vertical interconnect options for high-frequency system-in-package (SiP) integration: through encapsulant via (TEV) applied to the embedded wafer level ball grid array (eWLB) technology and through silicon via (TSV). We compare both solutions in terms of size and electrical performance. We use analytic expressions and electromagnetic simulations for our analysis and...
This paper presents a fully integrated 60GHz SiGe transceiver for industrial radar applications. The transceiver is packaged in an eWLB technology which allowes for direct embedding of two dipole antennas in the package. The compact transceiver frontend has been evaluated in an FMCW radar setup. The transceiver features a wide tunable operating range and is comprised of a vector modulator and a homodyne...
Through encapsulant vias (TEVs) are an interconnect technology which enables 3D stacking and double sided re-routing of packages encapsulated with epoxy molding compound. These interconnects are formed by Cu-plated holes through the encapsulant and can typically be routed by an RDL (redistribution layer). In order to enable prolonged function of these interconnects, thermo-mechanical reliability has...
In this paper, we present simulation and measurement results of single-ended and differential vertical interconnections realized using the thin-film redistribution layer (RDL) and through encapsulant vias (TEVs) of the embedded wafer level ball grid array (eWLB) package. We demonstrate that the fan-out area of the eWLB can be used advantageous for the design of passive devices using TEV structures...
Abstract Through encapsulant vias (TEVs) are an interconnect technology which enables 3D stacking and double sided re-routing of packages encapsulated with epoxy molding compound. These interconnects are formed by Cu-plated holes through the encapsulant and can typically be routed by an RDL (redistribution layer). In order to enable prolonged function of these interconnects, thermomechanical reliability...
We present for the first time a fully operational 77-GHz silicon-germanium (SiGe) single-chip four-channel transceiver module with four integrated antennas assembled in an embedded wafer-level ball grid array (eWLB) package. This eWLB module has a size of 8 mm × 8 mm and a footprint with a standard ball pitch of 0.5 mm. The module includes four half-wave dipole antennas that are realized using the...
The embedded wafer level ball grid array (eWLB) is a novel packaging technology that shows excellent performance for millimeter-wave (mm-wave) applications. We present simulation and measurement results of single-ended and differential transmission lines realized using the thin-film redistribution layers (RDL) of an eWLB. We demonstrate the capabilities for the integration of passives on example of...
We present a 5.9-to-7.8 GHz VCO in a 65 nm CMOS technology assembled in a chip-scale eWLB package. The VCO uses a high-quality LC-tank inductor, realized in the fan-out area of the package. Using this high-Q inductor the phase noise is reduced by as much as 9 dB at 1 MHz offset compared to a reference VCO, having on-chip inductor instead. The VCO using the eWLB inductor offers a phase noise of −118...
We investigate high-quality (high-Q) inductors realized in the fan-in area and in the fan-out area of the embedded wafer level ball grid array (eWLB) package. We show that the inductors realized in the fan-out area have negligible substrate losses and lower parasitic capacitances compared to the inductors in the fan-in area. As a result, the fan-out inductors offer significantly higher quality factors...
Fan-Out Wafer Level Packaging has arrived in the industry. The driving factors for the implementation of this packaging technology are the low packaging and test cost, the excellent electrical and thermal performance, the ability to work with increasing interconnect density on chip side and the potential for Integration of functionality. The increasing demand for new and more advanced electronic products...
Silicon front-end and assembly and packaging technology more and more merge. In addition interconnect density reaches limits for advanced CMOS technology. In this paper we introduce the fan-out embedded wafer level packaging technology, which is an example to link front-end and packaging technology and offers additional freedom for interconnect design. We demonstrate capabilites for system integration...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.