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A new technology concept of HVICs which realizes high negative surge immunity has been proposed for junction-isolation (JI) or self-isolation (SI) processes. The basic concept is to isolate a substrate from the ground level to block the surge current. A new 1200V-class HVIC based on the new concept has been fabricated. The new HVIC has shown more than 10x higher negative surge immunity.
A novel high-side well structure for a 1200V-class HVIC on a p-type substrate has been developed. The high-side well structure, consists of divided well regions with different voltage, makes it possible to integrate multiple circuits driven by different supply voltages on the high-side region in the HVIC. With implementing the developed structure, IGBT protection circuits on the high-side can be allocated...
In this paper, a new level up shifter with high dV/dt and negative transient voltage noise immunities is presented. The proposed level up shifter achieves high noise immunity without an increase in the delay time of high-voltage ICs (HVICs). A fabricated 1200V-class HVIC adopting the proposed level up shifter on a p-type substrate indicates a stable operation under the conditions of dV/dt noise over...
A simple low cost monolithic 3D through-silicon-via coreless transformer is designed and fabricated for high-voltage gate driver applications. The transformer comprises the primary coil embedded in the bottom layer of a Si substrate and the secondary coil built on the front-side of the substrate. Compared with conventional transformers with both coils built on the front-side or at the backside, the...
In this paper, a novel 3D TSV (Through-Silicon-Via) transformer technology for power system-on-chip applications is proposed and demonstrated experimentally. The transformer used in the power system features a galvanic isolation of > 4 kV and a voltage gain of > −3 dB from 10 MHz to 100 MHz. It can be embedded in the bottom layer of a silicon substrate and sandwiched between system circuitries...
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