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In this paper, we propose a novel Capacitance to Digital Converter (CDC) architecture using a second order continuous time delta-sigma modulator (CT-ΔΣM) with multi-bit quantization. The proposed architecture embeds a Capacitance to Voltage Converter (CVC) in the delta-sigma loop for improving the dynamic range and the energy efficiency of the CDC. VCO-integrator/multi-bit quantizer, used as one of...
This paper presents a fully integrated high precision Analog Front-End (AFE) as the readout IC for a MEMS capacitive open loop accelerometer. The design consists of continuous time Capacitance-to-Voltage Converter (CVC) followed by a low pass filter. It uses chopping technique to suppress low frequency 1/ƒ noise and achieve low offset. To ensure good PSRR and linearity the CVC employs a two stage...
This paper presents an Micro-Controller Unit (MCU) based ultra-low-power sensor signal processor design for a close-loop capacitive Micro-Electro-Mechanical Systems (MEMS) accelerometer. The proposed sensor signal processor provides basic sensor micro-system control and advanced signal processing functions, including analogue front-end configuration, digital delta-sigma modulation and decimation filtering...
This paper presents the system analysis, design and simulation of high performance seismic grade accelerometer interface. To date, all reported sigma-delta force feedback read out interfaces fall short of performance demanded by seismic grade instruments. In addition to the challenge of ensuring 20 bit resolution over a frequency band of few Hz to few hundred Hz, it has to achieve non-linearity in...
The digital compensation method for path delay mismatches in time-to-digital converter (TDC) based on gatedring oscillator (GRO) is proposed and demonstrated. The output of the GRO is digitized by the combination of a counter and a phase-to-digital converter producing an integer and a fractional digital value, respectively. Due to the delay mismatches between two paths, the integer and fractional...
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