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In this paper, we propose a novel Capacitance to Digital Converter (CDC) architecture using a second order continuous time delta-sigma modulator (CT-ΔΣM) with multi-bit quantization. The proposed architecture embeds a Capacitance to Voltage Converter (CVC) in the delta-sigma loop for improving the dynamic range and the energy efficiency of the CDC. VCO-integrator/multi-bit quantizer, used as one of...
This work proposes an ultra-low voltage, VCO-based sigma delta modulator with self-compensated current reference against process and temperature variations. The proposed current reference generator sets the feedback current of the multi-bit Non-Return-to-Zero (NRZ) DAC and the VCO tuning coefficient (KVCO) at ultra-low voltage. A test chip fabricated in 65nm CMOS technology demonstrated successful...
This paper introduces an ultra-low voltage open loop VCO-based ADC with background calibration for ultra-low power applications. A novel calibration scheme is proposed to calibrate the nonlinear voltage-to-frequency tuning curve of the VCO. A replica VCO is used to compute the correction coefficients and the corrected values are stored in a lookup table. The proposed calibration method is at least...
Quest for ultra-low power ADCs have forced researchers to push existing ADC architectures to work in ultra-low voltage supply. VCO based ADCs are promising solutions to address this problem since continuous scaling in CMOS technology aids their highly digital nature and time-based architectures. However, VCO-based ADCs have various challenges for achieving ultra-low power targets such as small voltage...
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