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In this paper, a 256×40 energy-efficient ternary content addressable memory (TCAM) macro is designed and implemented in 40nm low power (LP) CMOS. Due to the thicker gate oxide in LP process, a 16T TCAM cell with p-type comparison circuits is proposed to increase the Ion/Ioff difference of the dynamic circuitry. To further improve energy efficiency, don't-care-based ripple search-lines/bit-lines are...
Subthreshold SRAM is a significant approach to reduce power consumption in energy-constrained SoC design. For the ultra-low power consideration, the primary concerns of SRAM are stability and reliability instead of performance. In this paper, the proposed 9T bit-cell enhances write ability by cutting off the positive feedback loop of inverter pair. In the read mode, the isolated read path and storage...
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