The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
A low-power fully-integrated transceiver for K-band wireless communication was developed using 0.18 μm SiGe BiCMOS technology. Transformers are used to stack circuit blocks directly and to connect signals in multiple paths, and a balun is used to combine differential signals efficiently. These passive-interstage circuit schemes make it possible to reduce power dissipation without degradation in performance...
A low-power transmitter mixer and a receiver mixer operating in the K-band frequency region have been developed. Both mixers can be operated at a low supply voltage of 1.5 V because of a pseudo-stacked configuration using an on-chip transformer. For the transmitter mixer, an emitter degeneration resistor in parallel with a capacitor is introduced to obtain both high linearity and high-gain. Moreover,...
In this work, a 59 GHz push-push VCO is based on a new output circuit concept to simultaneously achieve both wide tuning range and high output power. It achieves a wide frequency tuning range of 13.9 GHz, high output power of 1.2 dBm, and low phase noise of-108 dBc/Hzat 1 MHz offset frequency. To the authors' knowledge, its figure of merit (FOMT) of -189.6 dB is the best for silicon-based 50 GHz class...
A full-rate 10 Gb/s transceiver core employing a tri-state binary PD with 100ps gated digital output is implemented in a 90nm CMOS process. Direct drive from the VCO is utilized to eliminate the 10GHz clock buffer current. The RX exhibits a recovered-clock jitter of 906fsrms and an input sensitivity of 5.9mVpp. The TX generates a jitter of 5mUIrms. The chip consumes 250mW.
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.