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A new technique for computing the truncated cube of an operand at length of power two is proposed, implemented, analyzed, and compared to existing techniques. The new proposed method is comparable to previously proposed methods that compute the cube of an operand in parallel. Post layout results are presented in a 65nm Application Specific Integrated Circuit implementation and are compared against...
A 4 kb fully differential 8-port SRAM bitcell array (6 read ports and 2 write ports) is presented in this paper. This 8-port SRAM provides simultaneous access, high system throughput and a great read static noise margin by isolating the read ports from storage nodes. At 0.4 V supply voltage, designed 8-port SRAM bitcell shows 123, 137 and 123 mV static noise margin during read, write and standby modes,...
This paper describes the design flow of the standard cell characterization on five different technologies and integration of its results with other VLSI tools processes that can be duplicated and implemented for the research and education in the academia. In this proposed work, one design flow is on non-fabricable technology of open-source false-technology FreePDK45 of 45 nm CMOS technology [1]. The...
This paper presents an optimization method for computing an optimum lookup table size for two well-known look up table elementary function approximation methods; Symmetric Table Additional Method (STAM) and Multipartite Table Method (MTM). Using a discrete optimization algorithm called Leapfrogging, this paper utilizes a method to find the best decomposition of the coefficients to optimize look up...
In this paper, a novel differential single-port 12T SRAM bitcell is presented. This bitcell uses a read buffer to eliminate read disturbance, improves the read stability and achieves read static noise margin equal to its hold static noise margin. Using a column-based select signal this bitcell provides a half-select free feature, facilitating a bit-interleaving structure to reduce multi-bit soft errors...
An 8T SRAM bitcell is presented to improve the read stability and writability of SRAM in scaled technologies and low voltages. The presented bitcell achieves a faster access time by increasing the read current by 21% compared to a 6T bitcell. The proposed 8T bitcell utilizes a differential operation, single port and one wordline, therefore, it does not require any architectural changes from 6T SRAM...
VLSI adders are critically important in digital designs since they are utilized in ALUs, memory addressing, cryptography, and floating-point units. Since adders are often responsible for setting the minimum clock cycle time in a processor, they can be critical to any improvements seen at the VLSI level.
This chapter gives a quick introduction to the Verilog language utilized throughout this book. The ideas presented in this text are designed to get the reader acquainted with the coding style and methodology utilized. There are many enhancements to Verilog that provide high-level constructs that make coding easier for the designer. However, the ideas presented in this book are meant to present computer...
Elementary functions are one of the most challenging and interesting arithmetic computations available today. Many of the advancements in this area result from mathematical theory that has spanned many centuries of work. Elementary functions are typically the referred to as the most commonly utilized mathematical functions such as sin, cos, tan, exponentials, and logarithms [Mul97].
This chapter discusses implementations for division. There are actually many different variations on division including digit recurrence, multiplicative-based, and approximation techniques. This chapter deals with the class of division algorithms that are digit recurrence. Multiplicative-based division algorithms are explored in Chapter 7. For digit recurrence methods, the quotient is obtained one...
Verilog HDL is a Hardware Description Language (HDL) utilized for the modeling and simulation of digital systems. It is designed to be simple, intuitive, and effective at multiple levels of abstraction in a standard textual format for a variety of different tools [IEE95]. The Verilog HDL was introduced by Phil Moorby in 1984 at the Gateway Design Automation conference. Verilog HDL became an IEEE standard...
In this chapter, multiplication datapath designs are explored. As opposed to previous chapters where a design consists of basic gates, the designs in this chapter and subsequent to this chapter utilize designs that are more complex. Consequently, many of the designs that are visited in this chapter and beyond start utilizing more and more of the previous designs made throughout the book. This is a...
This chapter presents methods for computing division by iteratively improving an initial approximation. Since this method utilizes a multiplication to compute divide it typically is called a multiplicative-divide method. Since multipliers occupy more area than addition or subtraction, the advantage to this method is that it provide quadratic convergence. Quadratic convergence means that number of...
The role of arithmetic in datapath design in VLSI design has been increasing in importance over the last several years due to the demand for processors that are smaller, faster, and dissipate less power. Unfortunately, this means that many of these datapaths will be complex both algorithmically and circuit wise. As the complexity of the chips increases, less importance will be placed on understanding...
Computer systems research is often inhibited by the availability of memory designs. Existing Process Design Kits (PDKs) frequently lack memory compilers, while expensive commercial solutions only provide memory models with immutable cells, limited configurations, and restrictive licenses. Manually creating memories can be time consuming and tedious and the designs are usually inflexible. This paper...
A novel single-port, fully differential 8-transistor (8T) SRAM bitcell that is tolerant to process variations and suitable for low-power operation is proposed in this paper. At 500mV supply voltage, the proposed 8T bitcell achieves 44% and 16% improvement in read Static Noise Margin (SNM) and Write Noise Margin (WNM), respectively, compared to the 6-Transistor (6T) bitcell. This 8T bitcell shows process...
Multiplication is an important mathematical operation in many microprocessor architectures. And, multipliers have evolved dramaticlly after the late 1970s and have gone through tremendous changes with an aim of reducing the area and delay. This paper presents and an extension to Booth-3 multiplication architecture by implementing the partial product matrix in redundant form. It is anticipated that...
This paper discusses an optimized double-precision floating-point multiplier that can handle both denormalized and normalized IEEE 754 floating-point numbers. Discussions of the optimizations are given and compared versus similar implementations, however, the main objective is keeping compliant for denormalized IEEE 754 floating-point numbers while still maintaining high performance operations for...
This paper discusses modification to algorithms for computing within a parallel cubing unit. The algorithms discussed in this paper shows several architectures for various operand sizes ranging from 8 to 32 bits. The method proposed in this paper separates the cubing partial product matrix into smaller elements and organizes these partial products into repeatable manageable groups. Consequently, the...
In this paper, the authors proposed a novel technique to calculate the capacitance distribution and branching effort of a multiple fan-out logic path for equal propagation delay in each path regardless of number of gates and lengths of the wire segments in those logic path. The authors utilize the prior methods for the Unified Logical Effort (ULE) methodology as the basis of delay estimation and transistor...
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