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A 4 kb fully differential 8-port SRAM bitcell array (6 read ports and 2 write ports) is presented in this paper. This 8-port SRAM provides simultaneous access, high system throughput and a great read static noise margin by isolating the read ports from storage nodes. At 0.4 V supply voltage, designed 8-port SRAM bitcell shows 123, 137 and 123 mV static noise margin during read, write and standby modes,...
This paper describes the design flow of the standard cell characterization on five different technologies and integration of its results with other VLSI tools processes that can be duplicated and implemented for the research and education in the academia. In this proposed work, one design flow is on non-fabricable technology of open-source false-technology FreePDK45 of 45 nm CMOS technology [1]. The...
In this paper, a novel differential single-port 12T SRAM bitcell is presented. This bitcell uses a read buffer to eliminate read disturbance, improves the read stability and achieves read static noise margin equal to its hold static noise margin. Using a column-based select signal this bitcell provides a half-select free feature, facilitating a bit-interleaving structure to reduce multi-bit soft errors...
An 8T SRAM bitcell is presented to improve the read stability and writability of SRAM in scaled technologies and low voltages. The presented bitcell achieves a faster access time by increasing the read current by 21% compared to a 6T bitcell. The proposed 8T bitcell utilizes a differential operation, single port and one wordline, therefore, it does not require any architectural changes from 6T SRAM...
Computer systems research is often inhibited by the availability of memory designs. Existing Process Design Kits (PDKs) frequently lack memory compilers, while expensive commercial solutions only provide memory models with immutable cells, limited configurations, and restrictive licenses. Manually creating memories can be time consuming and tedious and the designs are usually inflexible. This paper...
A novel single-port, fully differential 8-transistor (8T) SRAM bitcell that is tolerant to process variations and suitable for low-power operation is proposed in this paper. At 500mV supply voltage, the proposed 8T bitcell achieves 44% and 16% improvement in read Static Noise Margin (SNM) and Write Noise Margin (WNM), respectively, compared to the 6-Transistor (6T) bitcell. This 8T bitcell shows process...
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