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The paper presents CMOS ASICs which can tolerate the single event upsets (SEUs), the single event transients (SET), and the single event latchup (SEL). Triple and double modular redundant (TMR and DMR) circuits in combination with SEL protection switches (SPS) make the base of the proposed approach. The SPS had been designed, characterized, and verified before it became a standard library cell. A...
The paper presents triple and double modular redundant (TMR and DMR) circuits with the latchup protection. Additional logic has been designed to control the latchup protection phase and different power domains. An analytical model for the failure-free probability estimation has been developed too. Test circuits have been implemented and simulated.
The paper presents a design flow for fault-tolerant CMOS ASICs which are immune to the single event upsets (SEU), the single event transients (SET), and the single event latchup (SEL). Triple and double modular redundant (TMR and DMR) circuits and SEL protection switches (SPS) make the base for design of the highly reliable ASIC. The SPS had been designed, characterised, and verified before it became...
This work reports the bipolar resistive switching behavior of more than 100 back-end-of-line (BEOL) integrated 600×600nm2 TiN/HfO2/Ti/TiN MIM devices in a 4 kbit memory array. Reliable current-voltage switching characteristics were only observed for devices with a thickness ratio of 1 (10 nm HfO2/10nm Ti), indicating the importance of the interface chemistry of the Ti/HfO2 interface. Moreover, the...
The paper describes the design, implementation, and verification of a system-on-chip aimed to play the role of a general purpose processor for a wireless body area sensor network node. The heart of the sensor node is the IPMS430 processor core. This processor core is a clone of the Texas Instruments MSP430 microcontroller's central processing unit. The implemented and verified system includes the...
The paper presents a case study on the implementation of LEON-2 processor system on a chip. LEON-2 core is used as a general purpose processor for the concept of high-performance low-power wireless engine. The implemented processor system has been verified and become a reusable module of our modular library. The measured speed and power consumption of implemented system on a chip prove LEON-2 processor...
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