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Because the hardware realization of cryptographic systems is more and more attractive in terms of their performance, and since hardware implementations can be favorable adapted with self-testing techniques, in this paper we present a hardware offline error detection methodology protecting the Galois Field inversion modules of the Advanced Encryption Standard. The proposed test solution is built around...
This paper presents a series of Built-In Self-Test architectures designed for the IDEA NXT family of crypto-algorithms implemented in crypto-chips. The proposed error-detection schemes are capable of verifying the integrity of the crypto-chip in an autonomous, non-concurrent manner. One of the testing solutions consists of stimulating the algorithm with test vectors generated by the IDEA NXT core...
An iterative, single precision, floating point multiplier is described in this paper, designed and verified using the Verilog description language. The design is provided for educational use, complementing the practical activity in Computer Architecture related courses. The area overhead of the architecture is reduced by resorting to shift-and-add multiplication, allowing to conveniently storing the...
An, offline fault detection strategy for the finite field inversion operation of Advanced Encryption Standard (AES) is presented in this paper. The AES inversion units are stimulated using conventional Test Pattern Generation methods and the results' correctness is evaluated by means of signature analysis. The proposed architecture rely on connecting several inversion operation together in order to...
A pseudo random test strategy for the AES is presented in this paper, suitable for fault tolerant cryptographic designs. The proposed solution is capable of assessing the integrity of a crypto-chip in a non-concurrent, autonomous manner. The error detection strategy relies on iterated execution of the crypto-system's components in order to reduce the complexity of the test architecture and the test...
This paper introduces a novel hardware implementation of the IDEA NXT encryption algorithm resistant to attacks, and proposes a strategy for testing the implementation on an Altera DE2 FPGA. The proposed design is analysed with respect to execution time and throughput, revealing its effectiveness in comparison to conventional approaches. Also, its performance in terms of execution time and throughput...
This research provides an efficient solution for protecting the multiplicative inversion module of the Advanced Encryption Standard (AES) against fault attacks. Two architectures are constructed based on the mathematical property of inversion operation, thus allowing an efficient test process to be derived for the hardware implementation of AES. Additionally, the structures are suitable for integration...
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