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This paper presents a series of Built-In Self-Test architectures designed for the IDEA NXT family of crypto-algorithms implemented in crypto-chips. The proposed error-detection schemes are capable of verifying the integrity of the crypto-chip in an autonomous, non-concurrent manner. One of the testing solutions consists of stimulating the algorithm with test vectors generated by the IDEA NXT core...
A pseudo random test strategy for the AES is presented in this paper, suitable for fault tolerant cryptographic designs. The proposed solution is capable of assessing the integrity of a crypto-chip in a non-concurrent, autonomous manner. The error detection strategy relies on iterated execution of the crypto-system's components in order to reduce the complexity of the test architecture and the test...
This paper introduces a novel hardware implementation of the IDEA NXT encryption algorithm resistant to attacks, and proposes a strategy for testing the implementation on an Altera DE2 FPGA. The proposed design is analysed with respect to execution time and throughput, revealing its effectiveness in comparison to conventional approaches. Also, its performance in terms of execution time and throughput...
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