The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
As the modern computing systems become increasingly embedded and portable, a growing set of applications in media processing (graphics, audio, video, and image) has evolved. Multiplication is the operation that is most often used in these applications which when accomplished in logarithmic number system results in an area efficient and faster design. In this work, the authors describe a technique...
Recent studies have demonstrated the potential for achieving higher area and power saving with approximate computation in error tolerant applications involving signal and image processing. Multiplication is a major mathematical operation in these applications which when performed in logarithmic number system results in faster and energy efficient design. In this paper, the authors present a method...
Digital comparators are key data path elements for a wide range of applications such as graphics and image processing. Existing designs either consume more power or tend to have large delay. To mitigate these issues, in this brief a new hybrid comparator scheme is proposed, which based on the input operands, selects the most efficient configuration for performing comparison operation. Experimental...
This paper presents a unified logic for flagged prefix addition-subtraction that eliminates the need to perform constant addition and subtraction in two separate blocks. The logic is based on a modified algorithm for constant subtraction that allows us to achieve the unification which is not possible with traditional algorithms. Thus we are able to eliminate the most crucial challenge that practical...
This paper presents a new architecture for a 7-bit Binary to BCD (BD) converter which forms the core of our proposed high speed decimal Multi-operand Adder. Our proposed design contains various improvements over existing architectures. These include an improved 7-bit BD Converter that helps in reducing the delay of the Multi-operand decimal Adder. Simulation results indicate that with a marginal increase...
This paper presents an unsigned truncated recursive multiplier architecture based on the variable correction method. The proposed design can be partitioned to perform as one N-bit fixed width multiplier or as two N/2-bit full precision multipliers. Design targets single level recursive multiplier architecture. Exhaustive analysis was carried out to calculate the maximum error bound in case of truncated...
This paper presents a twin precision multiplier with modified 2-D bypass Logic. The multiplier can perform one 8-bit multiplication or two 4-bit multiplications. The multiplier structure is modified by adding a 2-dimensional modified bypassing logic resulting in reduction in dynamic power as well the delay. Simulation results indicate that with a marginal increase in area, the proposed twin precision...
This paper presents a Reconfigurable Parallel Prefix Ling Adder. The proposed design can be partitioned to perform as one 16 bit, two 8 bit and four 4 bit adders. We also propose a new architecture for Enhanced Flagged Binary Adder (EFBA) designs which reduces the delay of operation considerably. The new adders are, therefore, modifications of conventional Reconfigurable Carry Lookahead Adder (CLA)...
This paper presents a design of prefix grouping based reversible comparator. Reversible computing has emerged as promising technology having its applications in emerging technologies like quantum computing, optical computing etc. The proposed reversible comparator design consists of three stages. The first stage consists of a 1-bitcomparator where two outputs, gi indicating Ai > Bi and eiindicating...
Reversible computing has emerged as promising technology having its applications in quantum computing, nanotechnology and optical computing. This paper presents design and analysis of reversible ripple, prefix and prefix ripple hybrid adders. Firstly an analysis and comparison of all the existing reversible ripple carry adders is presented. The reversible ripple carry adders are characterized by high...
This paper presents a new improved multiplexer based decoder for flash analog-to-digital converters. The proposed decoder is based on 2:1 multiplexers. It calculates the binary code for low operand length thermometer code at initial stages and groups the output of initial stages to generate the final result. The proposed decoder can be configured to operate on thermometer code with reduced length...
An Increment/Decrement circuit is a common building block in many digital systems like address generation unit which are used in micro controllers and microprocessors. Similarly 2's complement and priority encoder circuits are used in many applications. This paper presents an improvement to the decision block of the existing INC/DEC architectures. This improvement results in up to 48% reduced delay...
In this paper a new reconfigurable architecture for efficient Binary coded decimal (BCD) addition/subtraction is presented. The architecture is mainly designed keeping in mind the signed magnitude format. The proposed architecture avoids the usage of additional 2's complement and 10's complement circuitry, for correcting the results to sign magnitude format. The architecture is run-time reconfigurable...
Algorithms based Media applications operate on operands of varying data lengths. Although much work has been done in designing adder and multiplier architectures which operate on varying data lengths, there has been little work on implementing other operations like increment/decrement, 2's complement etc. This paper presents an architecture which can perform increment/decrement/2's complement/priority-encode...
The need to have hardware support for decimal arithmetic is increasing in recent years because of the growth in the decimal data processing in commercial, financial and internet based applications. In this paper a new architecture for efficient Binary coded decimal (BCD) addition/subtraction is presented that can be reconfigured to perform binary addition/subtraction. The architecture is mainly designed,...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.