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This paper describes a new full-chip CDM ESD verification method that enables the evaluation of complete integrated circuits (ICs) for CDM risk. We demonstrate that a robust analysis must comprehend millions of locations of driver-receiver (D/R) pairs on an IC, an accurate model of the grid resistance and an adequate representation of the CDM current distribution.
A new software tool, P2P, for electrical simulation of power nets is presented. The Rmap functionality of P2P calculates resistances from specified starting points to all points on the net, and visualizes the results in resistance color maps - which enables quick identification and debugging of layout errors. P2P also enables point-to-point resistance calculation, IR voltage drop analysis, and current...
A new EDA tool suite is presented for layout verification of ESD protection networks. It uses novel methodologies to accurately analyze interconnect resistance and current density, enabling quick identification of ESD weak areas at chip, block and detailed cell levels. The suite also includes a precision capacitance extraction tool.
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