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Recent advances and new trends in high voltage SiC based MOSFETs are analyzed. The main focus is done on design optimization strategies for reducing the on-state resistance. Gate oxide treatments for improving the interface quality resulting in a lower channel resistance are reviewed as well as solutions for lowering the JFET and bulk resistance components. The 3rd quadrant operation, short-circuit...
This paper presents an investigation regarding the influence of the active area design on the static and dynamic performance of SiC JBS diodes. The analysis has been performed on fabricated JBS diodes, rated for 1.7kV applications. For the active area layout, both stripe and hexagonal cell patterns have been used for the implanted p+ regions.
This paper presents an experimental investigation of the dynamic performance of SiC 6.5kV JBS diodes. Using a hybrid Si SPT IGBT/SiC JBS diodes combination, we have analyzed the turn-off behavior limits of SiC JBS diodes and compared the result against a state-of-the-art Si PiN diode. The experimental results show that the JBS diodes can handle about 40A/chip at 125°C before going into thermal runaway...
An approach to implement electrically robust MOSFETs in a functioning half-bridge will be investigated. For the first time, reverse conducting 3.3kV SiC MOSFETs have been fabricated with dilferent cell pitches from 14μm (p1.0) to 26μm (pl.8) that are able to withstand short circuit pulse of up to 10μs and a 9ms surge current event up to 15x the nominal current. LinPak half-bridge modules have been...
This paper reports a new edge termination for SiC power semiconductors. The novel concept, termed JTE (Junction Termination Extension) rings, combines the advantages of two classical termination techniques, namely floating p+ rings and JTE, to create a more efficient and robust edge termination. The new concept has been applied to large area (5×5mm2) Junction Barrier Schottky (JBS) diodes rated for...
The paper presents the feasibility of using gate-emitter voltage during IGBT turn-off in estimating the junction temperature of semiconductor chips in IGBT modules in real-time application. It is shown that the chosen parameter has negligible module and measurement circuit variation once calibrated and has been implemented successfully in a converter.
This paper discusses an elaborated study about the design of Junction-Barrier Schottky (JBS) diodes regarding the width (w) and spacing (s) of the implanted p+ pattern, utilizing epitaxial drift-layer specifications (4H-SiC) suitable for 1.7 kV applications. The impact of the w/s design-ratio on the blocking characteristics, the unipolar ON-state performance as well as moderation of surge current...
A novel method is presented for online estimation of the junction temperature (Tj) of semiconductor chips in IGBT modules, based on evaluating the gate-emitter voltage (Vge) during the IGBT switch off process. It is shown that the Miller plateau width (in the Vge waveform) depend linearly on the junction temperature of the IGBT chips. Hence, a method can be proposed for estimating the junction temperature...
The paper presents methods for the online estimation of the junction temperature (Tj) for IGBT modules with paralleled semiconductor chips, with each chip operating at different junction temperatures. Experimental and simulation results are presented. The Tj estimated from the gate-emitter voltage (Vge) during the IGBT switch off process was found to be very close to the average junction temperature...
The paper presents a novel method for online estimation of the junction temperature (Tj) of semiconductor chips in IGBT modules, based on evaluating the gate-emitter voltage (Vge) during the IGBT switch off process. It is shown that the Miller plateau width (in the Vge waveform) depend linearly on the junction temperature of the IGBT chips. Hence, a method can be proposed for estimating the junction...
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