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A 16-core processor with both message-passing and shared-memory inter-core communication mechanisms is implemented in 65 nm CMOS. Message-passing communication is enabled in a 3 6 Mesh packet-switched network-on-chip, and shared-memory communication is supported using the shared memory within each cluster. The processor occupies 9.1 and operates fully functional at a clock rate...
This paper presents an implementation of H.264 decoder on a 16-core processor. Multi-core architecture emerges as a good solution to tackle with substantially increasing computation complexity in media applications. A dramatic speedup can be achieved utilizing task-level, thread-level and data-level parallelism. As the core number increases, the inter-core communications draws more attention. We integrate...
Almost all multicore processors use a shared-memory architecture due to its simple programming model. Recently, however, the message-passing mechanism is also drawing attention due to its potentially better scalability [1–2]. In this work, we demonstrate that a hybrid communication mechanism supporting both message passing and shared memory can provide both higher performance and energy efficiency...
This paper presents a 32-bit vector multiply-accumulate (MAC) architecture capable of supporting multiple precisions. The vector MAC can perform one 32÷32, one 32÷16, two 16÷16, four 8÷8 bit signed/unsigned multiply-accumulate using Booth encoding algorithm and Wallace tree compressing. A reconfigurable Booth encoding array is implemented using 8÷8 Booth unit as the basic element, and longer bit modes...
Among current outstanding research problems in NoC Design, mapping application onto NoC is one of the core issues to be explored. In this paper, we propose two methods for mapping a pip elined flow chart onto mesh-based NoC system: Communication Length Concerned (CLC) method and Space Restricted (SR) method after a simple pre-process. The former significantly reduces the latency and energy consumption...
This paper proposes a novel multi-core processor with SIMD(Single Instruction Multiple Data) ISA (Instruction Set Architecture) and extended register file for communication applications. To acquire better parallel computing capability, we implement SIMD ISA and increase the number of register file from 32 to 64. 5×5 homogeneous 2-D mesh NoC (Network-on-Chip) topology is adopted to further enhance...
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