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Micro-Raman spectroscopy (μRS), finite element modelling, and electrical measurements of transistors used as stress-sensors, are used to study stress in a 3D-stacked IC. It is shown that the combination micro-bumps/underfill causes large stress variations in the silicon. Correlation of the three techniques shows that the effect of the different stress components and of X-sectioning on stress reduction...
In this work the effects of 3D stacking technology on the performance of devices are systematically studied. For this study a special chip consisting of a number of stress sensors and vertical interconnect loops was designed and manufactured in 65nm technology. Local variations of stress with a magnitude of up to 300 MPa are detected at different locations along the chip and are being characterized...
This work proposes an array-based evaluation circuit for efficient and massively parallel characterization of Bias Temperature Instability (BTI). This design is highly efficient when studying the BTI time-dependent variability in deeply-scaled devices, where hundreds of devices should be tested in order to obtain a statistically significant sample size. The circuit controls stress and measurement...
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