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In this paper we introduce an air-to-ground channel model extension for a multi-antenna system. The performance of an aeronautical communication system is strongly influenced by the presence of scatterers and by the three-dimensional (3-D) configuration of transmitter and receiver such as location and velocity. Combined statistical and geometrical models were used to offer a time-space description...
Network-on-Chip (NoC) have become favorable for on-chip communication, especially with the ever rising number of communication partners in future manycore system-on-chip. NoCs that are based on mesh topologies with dimension-routing are well-established as they scale well with the increasing number of communication partners and allow efficient router design. To be able to serve application demands...
Temporal runtime-reconfiguration of FPGAs allows for a resource-efficient sequential execution of signal processing modules. Approaches for partitioning processing chains into modules have been derived in various previous works. We will present a metric for weighted partitioning of pre-defined processing element sequences. The proposed method yields a set of reconfigurable partitions, which are balanced...
The exploration of the design space for complex hardware-software systems requires accurate models for the system components, which are often not available in early design phases, resulting in error-prone resource estimations. For a HWSW system with a finite set of design points, we present an analytical approach to evaluate the quality of a distinctive design point choice. Our approach enables the...
Demodulation and decoding of second generation terrestrial digital video broadcasting (DVB-T2) signals on general purpose processor platforms is challenging in terms of complexity and in terms of power. FPGA-based runtime acceleration for DVB-T2 allows for unwrapping the iterative structures of modern channel decoding schemes by using parallel hardware designs. Additionally, due to the sequential...
The sequential execution of processing elements by time-multiplexing FPGA resources using single-island partial reconfiguration allows for resource-efficient designs in comparison to static FPGA implementations. Designing a processing chain for such a system requires the chain to be partitioned into reconfigurable modules, which can be sequentially executed. For this task, we will present an approach...
Run-time reconfiguration of FPGAs has been around in academia for more than two decades but it is still applied very seldom in industrial applications. This has two main reasons: a lack of killer applications that substantially benefit from run-time reconfiguration and design tools that permit to quickly implement corresponding reconfigurable systems. This tutorial gives a survey on state-of-the-art...
The limited number of logic elements makes the implementation of signal processing chains on low-cost FPGAs a challenging task. In order to allow the implementation of complex designs on devices with limited resources, we propose the subpartitioning of a processing chain into several modules, which are loaded and executed in a round-robin fashion using dynamic partial reconfiguration (DPR) of FPGAs...
The performance of a DRM+ broadcast system using a modified Digital Video Broadcasting (DVB-T2/S2) Low Density Parity-Check (LDPC) code is compared against the standardized system, which uses convolutional coding. By using this modified LDPC code the datarate can be increased by 33 % at a similar bit error rate (BER) performance. Alternatively, the broadcast coverage can be increased. For the purpose...
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