The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
In this paper, high frequency measurement of TSV structures under different DC bias conditions are carried out. The impact of the MOS capacitance effect of TSV on its transmission performance is analyzed. Capacitance and conductance parameters of TSV are extracted and compared with numerical calculations.
Three-dimensional integration technology is deemed as the most promising alternative in post Moore's Law era. The electrical performance of through silicon vias (TSVs), which are the key enabler for 3D integration, is crucial to modeling and design of 3D systems, especially for high-speed systems. This paper gives a partial review on recent progress in the field with the focus on the high-frequency...
Along with extensive applications of through-silicon vias (TSVs) in 3-D systems, such as digital, logic, and memory modules, the accurate modeling of coupling capacitance between the TSVs is becoming indispensable to the signal integrity analysis of the system design. In this paper, the static characteristics of potential, electric field, and charges between signal-ground TSVs in a floating substrate...
This paper presented a method to examine the electrical characteristics of sidewall insulation layer of through silicon via (TSV), including breakdown voltage and sidewall capacitance. Blind via samples were fabricated for the experiment using deep reactive ion etching. 2μm SiO2 insulation layer was deposited using PECVD (Plasma enhanced chemical vapor deposition). Ti/W/Cu adhesive/barrier/seed layer...
As the speed of digital systems continues to increase, digital design has entered a new realm that requires high integration and high complexity with limited dimension. Different from the parameter analysis in low frequency which mainly focuses on resistances and their effects, the coactions of resistances, inductances and capacitances are all needed to be taken into account in high frequency. This...
Multi-gate devices are expected to enable continued scaling beyond the 32nm node in part due to their improved gate control of the channel versus planar MOSFETs. Static random access memory (SRAM) scaling, which requires increasing design margins despite decreasing layout area, may motivate the transition to a multi-gate architecture. Tri-gate bulk devices are an attractive multi-gate option because...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.